AD9251BCPZRL7 Analog Devices, Inc., AD9251BCPZRL7 Datasheet - Page 24

• Manufacturer Part Number: AD9251BCPZRL7
• Description: 14-bit, 20 Msps/40 Msps/65 Msps/80 Msps, 1.8 V Dual Analog-to-digital Converter
• Manufacturer: Analog Devices, Inc.

AD9251
The clock input should be treated as an analog signal in cases in
which aperture jitter may affect the dynamic range of the AD9251.
Separate power supplies for clock drivers from the ADC output
driver supplies to avoid modulating the clock signal with digital
noise. Low jitter, crystal-controlled oscillators make the best
clock sources. If the clock is generated from another type of source
(by gating, dividing, or another method), it should be retimed by
the original clock at the last step.
Refer to the AN-501 Application Note and the AN-756 Application
Note (see
performance as it relates to ADCs).
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 49, the power dissipated by the AD9251 is
proportional to its sample rate. In CMOS output mode, the
digital power dissipation is determined primarily by the
strength of the digital drivers and the load on each output bit.
The maximum DRVDD current (I
where N is the number of output bits (30, in the case of the
AD9251).
This maximum current occurs when every output bit switches on
every clock cycle, that is, a full-scale square wave at the Nyquist
frequency of f
established by the average number of output bits switching,
which is determined by the sample rate and the characteristics
of the analog input signal.
Reducing the capacitive load presented to the output drivers can
minimize digital power consumption. The data in Figure 49 was
taken using the same operating conditions as those used for the
Typical Performance Characteristics, with a 5 pF load on each
output driver.
By asserting PDWN (either through the SPI port or by asserting
the PDWN pin high), the AD9251 is placed in power-down
mode. In this state, the ADC typically dissipates 1.8 mW.
I
DRVDD
Figure 49. AD9251-80 Power and Current vs. Sample Rate
www.analog.com
= V
CLK
DRVDD
/2. In practice, the DRVDD current is
× C
LOAD
for more information about jitter
× f
CLK
× N
DRVDD
) can be calculated as
Rev. PrH | Page 24 of 36
During power-down, the output drivers are placed in a high
impedance state. Asserting the PDWN pin low returns the
AD9251 to its normal operating mode. Note that PDWN is
referenced to the digital output driver supply (DRVDD) and
should not exceed that supply voltage.
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering power-
down mode and then must be recharged when returning to normal
operation. As a result, wake-up time is related to the time spent
in power-down mode, and shorter power-down cycles result in
proportionally shorter wake-up times.
When using the SPI port interface, the user can place the Adc in
power-down mode or standby mode. Standby mode allows the
user to keep the internal reference circuitry powered when
faster wake-up times are required. See the Memory Map section
for more details.
DIGITAL OUTPUTS
The AD9251 output drivers can be configured to interface with
1.8 V to 3.3 V CMOS logic families.
The CMOS output drivers are sized to provide sufficient output
current to drive a wide variety of logic families. However, large
drive currents tend to cause current glitches on the supplies that
may affect converter performance.
Applications requiring the ADC to drive large capacitive loads
or large fanouts may require external buffers or latches.
The output data format can be selected for either offset binary
or twos complement by setting the SCLK/DFS pin when operating
in the external pin mode (see Table 11). As detailed in the
AN-877 Application Note, Interfacing to High Speed ADCs via
SPI, the data format can be selected for offset binary, twos
complement, or gray code when using the SPI control.
Table 11. SCLK/DFS Mode Selection (External Pin Mode)
Voltage at Pin
AGND
DRVDD
Digital Output Enable Function (OE)
The AD9251 has a flexible three-state ability for the digital
output pins. The three-state mode is enabled using the OE pin
or through the SPI interface. If the OE pin is low, the output
data drivers and DCOs are enabled. If the OE pin is high, the
output data drivers and DCOs are placed in a high impedance
state. This OE function is not intended for rapid access to the
data bus. Note that OE is referenced to the digital output driver
supply (DRVDD) and should not exceed that supply voltage.
SCLK/DFS
Offset binary (default)
Twos complement
Preliminary Technical Data
SDIO/DCS
DCS disabled
DCS enabled (default)