AD9251BCPZRL7 Analog Devices, Inc., AD9251BCPZRL7 Datasheet - Page 8

• Manufacturer Part Number: AD9251BCPZRL7
• Description: 14-bit, 20 Msps/40 Msps/65 Msps/80 Msps, 1.8 V Dual Analog-to-digital Converter
• Manufacturer: Analog Devices, Inc.

AD9251
SWITCHING SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS,
DCS disabled, unless otherwise noted.
Table 4.
Parameter
CLOCK INPUT PARAMETERS
DATA OUTPUT PARAMETERS
OUT-OF-RANGE RECOVERY TIME
1
2
Conversion rate is the clock rate after the CLK divider.
Wake-up time is dependent on the value of the decoupling capacitors.
Input Clock Rate
Conversion Rate
CLK Period --Divide-by-1 Mode (t
CLK Pulse Width High (t
Data Propagation Delay (t
DCO Propagation Delay (t
DCO to Data Skew (t
Pipeline Delay (Latency)
Aperture Delay (t
Aperture Uncertainty (Jitter, t
Wake-Up Time
Standby
2
CH A/CH B DATA
1
A
)
DCOA/DCOB
SKEW
CH
)
CLK+
CLK–
)
DCO
PD
VIN
CLK
)
)
J
)
)
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
N – 1
t
CH
Min
3
50/25
AD9251-20/AD9251-40
Figure 2. CMOS Output Data Timing
t
PD
N
t
Rev. Pr A| Page 8 of 36
t
A
Typ
TBD
TBD
TBD
0.1
9
1.0
0.1
500
500
TBD
CLK
t
DCO
t
SKEW
N – 9
N + 1
Max
625
20/40
N – 8
N + 2
Min
3
15.38
AD9251-65
N – 7
Typ
TBD
TBD
TBD
0.1
9
1.0
0.1
500
500
TBD
N + 3
Preliminary Technical Data
Max
625
65
N – 6
N + 4
Min
3
12.5
AD9251-80
N – 5
Typ
TBD
TBD
TBD
0.1
9
1.0
0.1
500
500
TBD
N + 5
Max
625
80
Unit
MHz
MSPS
ns
ns
ns
ns
Cycles
ns
ps rms
μs
ns
Cycles