AD9251BCPZRL7 Analog Devices, Inc., AD9251BCPZRL7 Datasheet - Page 11

• Manufacturer Part Number: AD9251BCPZRL7
• Description: 14-bit, 20 Msps/40 Msps/65 Msps/80 Msps, 1.8 V Dual Analog-to-digital Converter
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 8. Pin Function Description
Pin No.
0
1, 2
3
4, 5, 25, 26
6 to 9, 11 to 18, 20, 21
10, 19, 28, 37
22
23
24
27, 29 to 36, 38 to 42
43
44
45
46
47
48
49, 50, 53, 54, 59,
60, 63, 64
51, 52
55
56
57
58
Mnemonic
GND
CLK+, CLK−
SYNC
DNC
D0B to D13B
DRVDD
ORB
DCOB
DCOA
D0A to D13A
ORA
SDIO/DCS
SCLK/DFS
CS
OE
PDWN
AVDD
VIN±A
VREF
SENSE
VCM
RBIAS
(LSB) D0B
NOTES
1. NC = NO CONNECT
2. THE EXPOSED PADDLE MUST BE SOLDERED TO THE PCB GROUND
SPI Data ( Input/Output) Static enable for duty cycle stabilizer if not in SPI mode. 50 kΩ internal pull-down
Description
Exposed paddle is the only ground connection for the chip. Must be connected to PCB AGND.
Differential Encode Clock. PECL, LVDS, or 1.8 V CMOS inputs.
Digital Input. SYNC input to clock divider. 50 kΩ internal pull-down.
Do Not Connect.
Channel B Digital Outputs. D13B = MSB.
Digital Output Driver Supply (1.8 V to 3.3 V).
Channel B Out-of-Range Digital Output.
Channel B Data Clock Digital Output.
Channel A Data Clock Digital Output.
Channel A Digital Outputs. D13A = MSB.
Channel A Out-of-Range Digital Output.
in SPI mode. 50 kΩ internal pull-up in nonSPI mode.
SPI Clock. Static control of data output format, DFS, if not in SPI mode.
If high: twos complement.
If low: offset binary.
50 kΩ internal pull-down.
SPI Chip Select. Active low enable; 50 kΩ internal pull-up.
Digital Input. Enable Channel A and Channel B digital outputs if low, tristate outputs if high. 50 kΩ internal
pull-down.
Digital Input. Power-down chip if high. 50 kΩ internal pull-down.
1.8 V Analog Supply Pins.
Channel A Analog Inputs.
Voltage Reference Input/Output.
Reference Mode Selection.
Analog output voltage at midsupply to set common mode of the analog inputs.
Sets Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground.
TO ENSURE PROPER HEAT DISSIPATION, NOISE, AND MECHANICAL
STRENGTH BENEFITS.
DRVDD
SYNC
CLK+
CLK–
D1B
D2B
D3B
D4B
D5B
D6B
D7B
D8B
D9B
NC
NC
10
12
13
14
15
16
11
1
2
3
4
5
6
7
8
9
PIN 1
INDICATOR
Figure 5. Pin Configuration
Rev. PrH | Page 11 of 36
(Not to Scale)
AD9251
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PDWN
OE
CS
SCLK/DFS
SDIO/DCS
ORA
D13A (MSB)
D12A
D11A
D10A
D9A
DRVDD
D8A
D7A
D6A
D5A
AD9251