TS68302MAB Atmel Corporation, TS68302MAB Datasheet - Page 14

• Manufacturer Part Number: TS68302MAB
• Description: 16-bit Communication Controller, 16-20 MHz
• Manufacturer: Atmel Corporation

Table 8. AC Electrical Specifications
IMP Bus Master Cycles (see Figure 7, Figure 8 and Figure 9) f = 16.67 MHz (Continued)
Notes:
14
Num.
57A
58A
44
46
47
48
53
55
56
57
58
60
61
62
63
64
1. For loading capacitance of less than or equal to 50 pF, subtract 4 ns from the value given in the maximum columns.
2. Actual value depends on clock period.
3. When AS and R/W are equally loaded (±20%), subtract 5 ns from the values given in these columns.
4. If the asynchronous input setup (#47) requirement is satisfied for DTACK, the DTACK asserted to data setup time (#31)
5. The TS68302 will negate BG and begin driving the bus if external arbitration logic negates BR before asserting BGACK.
6. The minimum value must be met to guarantee proper operation. If the maximum value is exceeded, BG may be reasserted.
7. If #47 is satisfied for both DTACK and BERR, #48 may be ignored. In the absence of DTACK, BERR is a synchronous input
8. For power-up, the TS68302 must be held in the reset state for 100 ms to allow stabilization of on-chip circuit. After the sys-
9. Occurs on S0 of SDMA read/write access when the SDMA becomes bus master.
10. This specification is valid only when the RMCST bit is set in the SCR register.
TS68302
requirement can be ignored. The data must only satisfy the data-in to clock low setup time (#27) for the following clock cycle.
using the asynchronous input setup time (#47).
tem is powered up #56 refers to the minimum pulse width required to reset the processor.
Symbol
t
t
t
t
t
t
t
t
t
BELDAL
t
CHRMH
t
t
f
t
CHBCH
RMHGL
SHVPH
RLDBD
CHBCL
CLRML
CHDOI
HRPW
t
GASD
GAFD
RHSD
RHFD
t
GAL
ASI
Parameter
AS, DS negated to AVEC negated
BGACK width low
Asynchronous input setup time
BERR asserted to DTACK asserted
Data-out hold from clock high
R/W asserted to data bus impedance change
HALT/RESET pulse width
BGACK negated to AS, DS, R/W driven
BGACK negated to FC
BR negated to AS, DS, R/W driven
BR negated to FC
Clock high to BCLR asserted
Clock high to BCLR negated
Clock low (S0 falling edge during read) to RMC asserted
Clock high (S7 rising edge during write) to RMC negated
RMC negated to BG asserted
(5)
(8)
(9)
(10)
(4)
(5)
(2)(7)
Min
1.5
1.5
1.5
10
10
10
0
0
0
1
1
Max
50
30
30
30
30
30
2117A–HIREL–11/02
Unit
clks
clks
clks
clks
clks
clks
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns