TS68302MAB Atmel Corporation, TS68302MAB Datasheet - Page 31

• Manufacturer Part Number: TS68302MAB
• Description: 16-bit Communication Controller, 16-20 MHz
• Manufacturer: Atmel Corporation

Figure 24. GSI Timing Diagram
Table 21. AC Electrical Specifications - PCM Timing
There are two sync types:
Short frame - Sync signals are one clock cycle prior to the data.
Long frame - Sync signals are N-bits that envelope the data, N > 0.
Notes:
2117A–HIREL–11/02
Num.
300
301
302
303
304
305
306
307
308
309
310
311
1. The ratio CLK/TCLK1 must be greater than 2.5/1.
2. L1T x D becomes valid after the L1CLK rising edge or the sync enable, whichever is later, if long frames are used.
3. Specification valid for both sync methods.
4. See Figure 25.
L1SY0-L1SY1 hold time from L1CLK falling edge
Parameter
L1CLK (PCM clock) frequency
L1CLK width low/high
L1SY0-L1SY1 setup time to L1CLK falling edge
L1SY0-L1SY1 width low
Time between successive sync signals (short frame)
L1T x D data valid after L1CLK rising edge
L1T x D to high impedance (from L1CLK rising edge)
L1R x D setup time (to L1CLK falling edge)
L1R x D hold time (from L1CLK falling edge)
L1T x D data valid after syncs rising edge (long)
L1T x D to high impedance (from L1SY0-L1SY1 falling edge) (long)
(1)
(2)
(3)
(3)
(4)
(2)
f = 16.67 MHz
Min
55
20
40
20
50
1
8
0
0
0
0
Max
6.66
100
70
50
70
TS68302
L1CLK
L1CLK
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
31