TS68302MAB Atmel Corporation, TS68302MAB Datasheet - Page 38

• Manufacturer Part Number: TS68302MAB
• Description: 16-bit Communication Controller, 16-20 MHz
• Manufacturer: Atmel Corporation

System Control
System Control Register
Disable CPU Logic (68000)
Freeze Control
DRAM Refresh Controller
Communications
Processor
38
TS68302
The IMP system control consists of a system control register (SCR) containing bits for
the following system control functions:
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The SCR is a 32-bit register that consists of system status and control bits, a bus arbiter
control bit, hardware watchdog control bits, low power control bits, and freeze select
bits. The eight most significant bits of the SCR report events recognized by the system
control logic and set the corresponding bit in the SCR.
The low power modes are used, when no processing is required from the 68000/68008
core, to reduce the system power consumption to its minimum value. The low power
modes may be exited by an interrupt from an on-chip peripheral.
This control allows an external processor direct connection to the bus and to the IMP’s
peripherals while the on-chip 68000 core is disabled. Entered during a system reset
(RESET and HALT asserted together), this mode configures the IMP on-chip peripher-
als for use with other TS68032 units or other processors and is an effective
configuration for systems needing more than three SCCs.
This control is used to freeze the activity of selected peripherals and to debug systems.
The IMP freezes its activity with no new interrupt requests, no memory accesses (inter-
nal or external), and no access of the serial channels. The IDMA controller completes
any bus cycle in progress and releases bus ownership. No further bus cycles will be
started as long as FRZ remains asserted.
The CP main (RISC) controller can optionally handle the dynamic RAM (DRAM) refresh
task without any intervention from the 68000 core. The refresh request can be gener-
ated from a TS68302 timer, baud rate generator, or externally. The DRAM refresh
controller performs a standard 68000-type read cycle at programmable address
sequences, with user-provided RAS and CAS generation.
The CP in the TS68302 includes the main controller, six serial DMA channels, three
SCCs, an SCP, and two SMCs.
Host software configures each communications channel, as required by the application,
to include parameters, baud rates, physical channel interfaces desired, and interrupting
conditions. Buffer structures are set up for receive and transmit channels. Up to eight
frames may be received or transmitted without host software involvement. Selection of
the interrupt interface is also set by register bits in register space of the device.
Data is transmitted and received using the appropriate buffer descriptors and buffer data
space for a channel. The CP operates is a modified polling mode on each channel and
buffer descriptor to identify buffers awaiting transmission and channels requiring servic-
ing. The user sets a bit in the buffer descriptor of a transmit frame; when the CP polls
and detects this bit, it will begin transmission. Generally, no other action is required to
accomplish transmission.
system status and control logic,
bus arbitration logic with low interrupt latency,
hardware watchdog,
low power (standby) modes,
disable CPU logic (68000),
freeze control for debugging on-chip peripherals,
AS control during read-modify-write cycles.
2117A–HIREL–11/02