TS68302MAB Atmel Corporation, TS68302MAB Datasheet - Page 28

• Manufacturer Part Number: TS68302MAB
• Description: 16-bit Communication Controller, 16-20 MHz
• Manufacturer: Atmel Corporation

Table 18. AC Electrical Specifications - Serial Communication Port
Note:
Figure 22. Serial Communication Port Timing Diagram
Table 19. AC Electrical Specifications - Idle Timing
are referenced to the L1CLK at 50% point of VDD
28
Num.
Num.
250
251
252
253
254
260
261
262
263
264
265
266
267
268
269
270
271
272
273
1. This also applies when SPCLK is inverted by CI in the SPMODE register. The enable signals for the slaves may be imple-
2. See Figure 22.
TS68302
mented by the parallel I/O pins.
Parameter
SPCLK clock output period
SPCLK clock output rise/fall time
Delay from SPCLK to transmit
SCP receive setup time
SPC receive hold time
Parameter
L1CLK (IDL clock) frequency
L1CLK width low
L1CLK width high
L1T x D, L1RQ, SDS1-SDS2 rising/falling time
L1SY1 (sync) setup time (to L1CLK falling edge)
L1SY1 (sync) hold time (to L1CLK falling edge)
L1SY1 (sync) inactive before 4th L1CLK
L1T x D active delay (from L1CLK rising edge)
L1T x D to high impedance (from L1CLK rising edge)
L1R x D setup time (to L1CLK falling edge)
L1R x D hold time (from L1CLK falling edge)
Time between successive IDL syncs
L1RQ valid before falling edge of L1SY1
L1GR setup time (to L1SY1 falling edge)
(OUTPUT)
(OUTPUT)
(INPUT)
SPRXD
SPTXD
SPCLK
250
(1)
1
1
(1)
(1)
(1)
2
2
3
3
252
(3)
f = 16.67 MHz All timing measurements, unless otherwise specified,
(2)
253
4
4
251
(2)
f = 16.67 MHz
5
5
254
6
6
Min
Min
40
10
55
60
30
50
50
50
20
50
4
0
0
0
0
1
7
7
8
8
Max
Max
6.66
64
15
40
20
75
50
2117A–HIREL–11/02
L1CLK
L1CLK
MHz
Unit
Unit
clks
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns