MBM29BS12DH Fujitsu Media Devices, MBM29BS12DH Datasheet - Page 23

• Manufacturer Part Number: MBM29BS12DH
• Description: (MBM29FS12DH / MBM29BS12DH) BURST MODE FLASH MEMORY CMOS 128M (8M X 16) BIT
• Manufacturer: Fujitsu Media Devices

Asynchronous Read Operation (Non-Burst) Mode
Synchronous (Burst) Read Operation Mode
8-, 16-, and 32-Word Linear Burst with Wrap Around
8-word with wrap-around
16-word with wrap-around
32-word with wrap-around
FUNCTIONAL DESCRIPTION
When the device first powers up, it is enabled for asynchronous read operation. CLK is ignored in this operation.
To read data from the memory array, the system must first assert a valid address on A
and CE to V
low or the address transition while AVD is held low. The data will appear on DQ
array is divided into four banks, each bank remains enabled for read access until the command register contents
are altered.
Address access time (t
access time (t
enable access time (t
The internal state machine is set for reading array data in asynchronous mode upon device power-up, or after
a hardware reset. During power transition RESET must be held low. (Refer to "Power On/Off Timing Diagram")
This ensures that no spurious alteration of the memory content occurs during the power transition.
The device is capable of linear burst operation of a preset length.
Prior to entering burst mode, the system should determine how many wait states are desired for the initial word
(t
clock edge, and how the RDY signal will transition with valid data. The system would then write the configuration
register set command sequence. See "Configuration Register Set Command" and "Command Definitions" for
further details.
Once the system has written the "Configuration Register Set" command sequence, the device Read mode is
enabled for synchronous reads only.
The initial word is output t
the active edge of each successive clock cycle, which automatically increments the internal address counter.
The device provides Linear burst mode, in which a fixed number of words are read from consecutive addresses.
In each of these modes, the burst addresses read are determined by the group within which the starting address
falls. The groups are sized according to the number of words read in a single burst sequence for a given mode.
As an example: if the starting address in the 8-word with wrap-around mode is 39h, the address range to be
read would be 38-3Fh, and the burst sequence would be 39-3A-3B-3C-3D-3E-3F-38h-etc. The burst sequence
begins with the starting address written to the device, but wraps back to the first address in the selected group.
In a similar fashion, the 16-word and 32-word Linear Wrap modes begin their burst sequence on the starting
address written to the device, and then wrap back to the first address in the selected address group.
The RDY pin indicates when data is valid on the bus in synchronous read mode. The devices can wrap through
a maximum of 128 words of data (8 words up to 16 times, 16 words up to 8 times, or 32 words up to 4 times)
before requiring a new synchronous access (latching of a new address).
IACC
) of each burst access, what mode of burst operation is desired, which edge of the clock will be the active
Mode
IL
. WE should remain at V
CE
) is the delay from the stable addresses and stable CE to valid data at the outputs. The output
OE
) is the delay from the falling edge of OE to valid data at the output.
ACC
IACC
) is equal to the delay from stable addresses to valid output data. The chip enable
after the active edge of the first CLK cycle. Subsequent words are output t
IH
Group Size
Burst Address Groups Table
. The addresses are latched on the falling edge of CE while AVD is held
16 words
32 words
8 words
0h-7h, 8h-Fh, 10h-17h, ...
0h-Fh, 10h-1Fh, 20h-2Fh, ...
00h-1Fh, 20h-3Fh, 40h-5Fh, ...
MBM29BS/FS12DH
Group Address Ranges
15
to DQ
22
to A
0
. Since the memory
0
, while driving AVD
BACC
after
15
23