MBM29BS12DH Fujitsu Media Devices, MBM29BS12DH Datasheet - Page 32

• Manufacturer Part Number: MBM29BS12DH
• Description: (MBM29FS12DH / MBM29BS12DH) BURST MODE FLASH MEMORY CMOS 128M (8M X 16) BIT
• Manufacturer: Fujitsu Media Devices

32
MBM29BS/FS12DH
Read/Reset Command
Configuration Register Set Command
Read Mode Setting
Programmable Wait State Configuration Setting
COMMAND DEFINITIONS
Device operations are selected by writing specific address and data sequences into the command register. Some
commands require Bank Address (BA) input. When command sequences are input into a bank reading, the
commands have priority over the reading. “MBM29BS/FS12DH Command Definitons Table” shows the valid
register command sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h) commands are
valid only while the Sector Erase operation is in progress. Moreover, Read/Reset commands are functionally
equivalent, resetting the device to the read mode. Please note that commands are always written at DQ
and DQ
In order to return from Autoselect mode or Exceeded Timing Limits (DQ
of secter protect commands the Reset operation is initiated by writing the Reset command sequence into the
command register. Microprocessor read cycles retrieve array data from the memory. The device remains enabled
for reads until the command register contents are altered.
The device will automatically power-up in the Asynchronous Read/Reset state. In this case, a command se-
quence is not required to read data. Standard microprocessor read cycles will retrieve array data. Refer to the
AC Read Characteristics and Waveforms for specific timing parameters.
The device uses a configuration register to set the various burst parameters: number of wait states, burst read
mode(burst length), active clock edge, RDY configuration, and synchronous mode active. The configuration
register must be set before the device will enter burst mode.
The configuration register is loaded with a three-cycle command sequence. The first two cycles are standard
unlock sequences. On the third cycle, the data should be C0h, address bits A
bits A
setting, which is in asynchronous mode. The register must be set before the device can enter synchronous
mode. The configuration register can not be changed during device operations (program, erase, or New Sector
Protection).
On power-up or hardware reset, the device is set to be in asynchronous read mode. This setting allows the
system to enable or disable burst mode during system operations. Address A
asynchronous mode, "0" for synchronous mode.
The programmable wait state feature informs the device of the number of clock cycles that must elapse after
AVD is driven active before data will be available. This value is determined by the input frequency of the device.
Address bits A
sequence instructs the device to set a particular number of clock cycles for the initial access in burst mode. The
number of wait states that should be programmed into the device is directly related to the clock frequency.
19
15
to A
A
0
0
0
0
1
1
1
1
14
to DQ
12
set the code to be latched. The device will power up or after a hardware reset with the default
14
8
to A
bits are ignored.
12
determine the setting (see “Third Cycle Address/Data Table”). The wait state command
A
0
0
1
1
0
0
1
1
13
Third Cycle Address/Data Table
15
A
0
1
0
1
0
1
0
1
12
5
= 1) to Read/Reset mode, verify mode
11
19
Total Initial Access Cycles
to A
determines this setting: "1’ for
0
should be 555h, address
Reserved
Reserved
2
3
4
5
6
7
7
to DQ
0