MBM29BS12DH Fujitsu Media Devices, MBM29BS12DH Datasheet - Page 68
MBM29BS12DH
Manufacturer Part Number
MBM29BS12DH
Description
(MBM29FS12DH / MBM29BS12DH) BURST MODE FLASH MEMORY CMOS 128M (8M X 16) BIT
Manufacturer
Fujitsu Media Devices
Datasheet
1.MBM29BS12DH.pdf
(84 pages)
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68
MBM29BS/FS12DH
Notes :
Address
Data
AVD
CLK
WE
V
CE
OE
CC
PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
"In progress" and "complete" refer to status of program operation.
A
Configuration Register is set to Synchronous mode.
Addresses are latched on the first of either the falling edge of WE or active edge of CLK.
When "t
22
t
AVSW
Figure 20
to A
t
t
CS
AS
555h
12
WLC
t
VCS
are don’t care during command sequence unlock cycles.
t
" is not met then AVD/address set up and hold time to CLK will be required.
AH
t
Program Command Sequence (last two cycles)
WP
t
t
AVHW
WLC
Program Operation Timings at Synchronous Mode (WE latch)
t
A0h
WC
t
WPH
PA
15
t
DS
PD
t
DH
t
CH
VA
t
WHWH1
Progress
Read Status Data
In
VA
Complete
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