MBM29BS12DH Fujitsu Media Devices, MBM29BS12DH Datasheet - Page 26

• Manufacturer Part Number: MBM29BS12DH
• Description: (MBM29FS12DH / MBM29BS12DH) BURST MODE FLASH MEMORY CMOS 128M (8M X 16) BIT
• Manufacturer: Fujitsu Media Devices

26
MBM29BS/FS12DH
Standby Mode
Automatic Sleep Mode
Output Disable
Write
There are two ways to implement the standby mode on the device, one using both the CE and RESET pins, and
the other via the RESET pin only.
When using both pins, a CMOS standby mode is achieved with CE and RESET input held at V
this condition the current consumed is less than 10 µA Max. During Embedded Algorithm operation, V
current (I
these standby modes.
When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at V
or “L”) . Under this condition the current consumed is less than 5µA Max. Once the RESET pin is set high, the
device requires t
During standby mode, the output is in the high impedance state, regardless of OE input.
I
Automatic sleep mode works to restrain power consumption during read-out of the device data. This mode can
be useful in the application such as a handy terminal which requires low power consumption.
While in asynchronous mode, the device automatically enables this mode when addresses remain stable for
t
access timings provide new data when addresses are changed. While in sleep mode, output data is latched and
always available to the system. Under the mode, the current consumed is typically 0.2 A (CMOS Level). Since
the data are latched during this mode, the data are continuously read out. When the addresses are changed,
the mode is automatically canceled and the device reads the data for changed addresses.
While in synchronous mode, the device automatically enables this mode when the first active CLK level (if rising
edge is acitive, the first period of CLK=V
latency will be same between even and odd address. The device always outputs data with the same latency to
even address. In case of Non-Handshaking devices, initial latecny is fixed same as normal operation. When the
deivce is in the Automatic sleep mode, the device outputs burst data with the CLK. Please note that if CLK runs
faster (active CLK level is shorter than t
output incorrect data. In this case, a new burst operations (addresses must be re-latched) is required to provide
correct data. Under the mode, the current consumed is typically TBD A (CMOS Level).
During simultaneous operation, V
When the OE input is at V
state.
Device erasure and programming are accomplished via the command register. The contents of the register serve
as input to the internal state machine. The state machine output dictates the function of the device. The command
register itself does not occupy any addressable memory location. The register is a latch used to store the
commands, along with the address and data information needed to execute the command. The programming
operation is dependent of the Set Device Read Mode bit in the Configuration Register.
- At Asynchronous Mode
Clock is ignored when the Configuration Register is set to Asynchronous mode, the device has the capability of
performing two types of programming operation.
WE latch - The system must drive CE, WE, and AVD to V
Addresses are latched on the falling edge of WE while data is latched on the rising edge of WE. (Refer to
"Program Operation Timing at Asynchronous Mode (WE latch)").
AVD latch - The system must drive CE and AVD to V
and drive WE and CE to V
and data is latched on the rising edge of WE. (Refer to "Program Operation Timing at Asynchronous Mode (AVD
latch)").
CC3
ACC
+60 ns. The automatic sleep mode is independent of the CE, WE, and OE control signals. Standard address
in the DC Characteristics table represents the standby current specification.
CC2
) is required even if CE=“H”. The device can be read with standard access time (t
RH
as a wake-up time for output to be valid for read access.
IH
IL
, and OE to V
, output from the device is disabled. The outputs are placed in the high impedance
CC
active current (I
15
IH
ACC
) is greater than t
IH
) during burst access in the Automatic speep mode, the device will
when wiring data. Addresses are latched on the rising edge of AVD
CC2
IL
, and OE to V
) is required.
IL
ACC
and OE to V
. During this mode on Handshaking devices, initial
IH
when providing an address to the device,
IH
when providing an address and data.
SS
CE
CC
±0.3 V (CE=“H”
) from either of
±0.2 V. Under
CC
active