MBM29BS12DH Fujitsu Media Devices, MBM29BS12DH Datasheet - Page 27

• Manufacturer Part Number: MBM29BS12DH
• Description: (MBM29FS12DH / MBM29BS12DH) BURST MODE FLASH MEMORY CMOS 128M (8M X 16) BIT
• Manufacturer: Fujitsu Media Devices

Hardware Reset
Accelerated Program Operation
HiddenROM Region
RESET
- At Synchronous Mode
When the Configuration Register is set to Synchronous mode, the device has the capability of performing two
types of programming operation.
WE latch - The system must drive CE, WE, and AVD to V
Addresses are latched on the falling edge of WE while AVD is held V
WE. (Refer to "Program Operation Timing at Synchronous Mode (WE latch)"). Refer to AC Write Characteristics
and the Erase/Program Waveforms for specific timing parameters.
Note : Addresses are latched on the first of either the falling edge of WE or active edge of CLK.
CLK latch - The system must drive CE and AVD to V
and drive WE and CE to V
while AVD is held VIL and data is latched on the rising edge of WE. (Refer to "Program Operation Timing at
Synchronous Mode (CLK latch)").
The device may be reset by driving the RESET pin to V
be kept low (V
of being executed will be terminated and the internal state machine will be reset to the read mode “t
the RESET pin is driven low. Furthermore, once the RESET pin goes high the device requires an additional “t
before it will allow read access. When the RESET pin is low, the device will be in the standby mode for the
duration of the pulse and all the data output pins will be tri-stated. If a hardware reset occurs during a program
or erase operation, the data at that particular location will be corrupted.
The device offers accelerated program operation which enables the programming in high speed. If the system
asserts V
program operation will reduce to about 60%. This function is primarily intended to allow high speed program,
so caution is needed as the sector group will temporarily be unprotected.
When at V
The system would use a fast program command sequence when programming during acceleration mode.
Set command to fast mode and reset command from fast mode are not necessary. When the device enters the
acceleration mode, the device automatically set to fast mode. Therefore, the pressent sequence could be used
for programming and detection of completion during acceleration mode.
Removing V
while programming. See “Accelerated Fast mode Programming Timing” in “ TIMING DIAGRAM”.
The HiddenROM feature provides a Flash memory region that the system may access through a new command
sequence. This is primarily intended for customers who wish to use an Electronic Serial Number (ESN) in the
device with the ESN protected against modification. Once the HiddenROM region is protected, any further
modification of that region becomes impossible. This ensures the security of the ESN once the product is shipped
to the field. ONLY Program is possible in this area until it is protected. Once it is protected, it is impossible to
unprotect, so please use this with caution.
HiddenROM area is 128 words (64 words for factory and 64 words for customer) in length and is stored at the
same address of the "outermost" 4 Kwords boot sector. The device occupies the address of the 000000h -
00007Fh. After the system has written the Enter HiddenROM command sequence, the system may read the
HiddenROM region by using the addresses normally occupied by the boot sector (particular area of SA0). That
is, the device sends all commands that would normally be sent to the boot sector to the HiddenROM region.
This mode of operation continues until the system issues the Exit HiddenROM command sequence, or until
power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending
commands to the boot sector.
ACC
IL
, ACC locks all sectors. Should be at V
ACC
to the ACC pin, the device automatically enters the acceleration mode and the time required for
IL
) for at least “t
from the ACC pin returns the device to normal operation. Do not remove V
IL
, and OE to V
RP
” in order to properly reset the internal state machine. Any operation in the process
IH
when wiring data. Addresses are latched on the active edge of clock
IH
IL
for all other conditions.
, and OE to V
IL
. The RESET pin has a pulse requirement and has to
IL
and OE to V
MBM29BS/FS12DH
IH
IL
when providing an address to the device,
and data is latched on the rising edge of
IH
when providing an address and data.
ACC
from ACC pin
READY
” after
RH
15
”
27