MBM29BS12DH Fujitsu Media Devices, MBM29BS12DH Datasheet - Page 9

• Manufacturer Part Number: MBM29BS12DH
• Description: (MBM29FS12DH / MBM29BS12DH) BURST MODE FLASH MEMORY CMOS 128M (8M X 16) BIT
• Manufacturer: Fujitsu Media Devices

(Continued)
Legend:
RA
PA
SA
BA
RD
PD
SGA
SD
HRA
HRBA
RD (0)
RD (1)
OPBP
PWA/PWD
PL
SPML
WP
WPE
CR
Password Verify
Password Mode
Locking Bit
Program
Persistent
Protection Mode
Locking Bit
Program
PPB Program
PPB Verify
All PPB Erase
PPB Lock Bit
Set
PPB Lock Bit
Verify
DPB Write
DPB Erase
DPB Verify
Command
Sequence
Address of the memory location to be read.
Address of the memory location to be programmed. Addresses latch on the rising edge of the AVD
pulse or active edge of CLK while AVD = V
AVD = V
Address of the sector to be erased. The combination of A
and A
Bank Address. Address settled by A
Data read from location RA during read operation.
Data to be programmed at location PA. Data latches on the rising edge of write pulse.
Sector group address to be protected.
Sector group protection verify data.
Output 01h at protected sector group addresses and output 00h at unprotected sector group
addresses.
Address of the HiddenROM area 000000h to 00007Fh
Bank Address of the HiddenROM area (A
Read Data bit. If programmed, DQ
Read Data bit. If programmed, DQ
Password Address/Password Data
Configuration Register address bits A
(A
(A
(A
(A
(A
7
7
7
7
7
, A
, A
, A
, A
, A
Cycles
Req’d
Write
12
Bus
6
6
6
6
6
, A
, A
, A
, A
, A
4
6
6
6
4
6
6
4
4
4
4
will uniquely select any sector.
IL.
5
5
5
5
5
, A
, A
, A
, A
, A
Addr.
555h AAh 2AAh 55h
555h AAh 2AAh 55h
555h AAh 2AAh 55h
555h AAh 2AAh 55h
555h AAh 2AAh 55h
555h AAh 2AAh 55h
555h AAh 2AAh 55h
555h AAh 2AAh 55h
555h AAh 2AAh 55h
555h AAh 2AAh 55h
555h AAh 2AAh 55h
4
4
4
4
4
First Bus
, A
, A
, A
, A
, A
Cycle
Write
3
3
3
3
3
, A
, A
, A
, A
, A
Data
2
2
2
2
2
, A
, A
, A
, A
, A
1
1
1
1
1
, A
, A
, A
, A
, A
Write Cycle
Addr.
Second
0
0
0
0
0
) is (0, 0, 0, 1, 1, 0, 1, 0)
) is (0, 0, 0, 0, 1, 0, 1, 0)
) is (0, 0, 0, 1, 0, 0, 1, 0)
) is (0, 0, 0, 0, 0, 0, 1, 0)
) is (0, 1, 0, 0, 0, 0, 1, 0)
Data
0
1
= 1, if erase, DQ
= 1, if erase, DQ
22
19
, A
Third Write
Addr. Data
555h C8h
555h
555h
555h
555h
555h
555h
555h
555h
555h
555h
(BA)
to A
21
Cycle
22
IL
, A
= A
whichever comes first or falling edge of write pulse while
12
20
60h
60h SPML 68h SPML 48h
60h
90h
60h
78h
58h
48h
48h
58h
.
will select Bank A, Bank B, Bank C and Bank D.
21
= A
SGA+
SGA+
Write Cycle
Addr.
PWA PWD
WPE
WP
WP
SA
SA
SA
SA
PL
—
20
0
1
Fourth
= 0
= 0
MBM29BS/FS12DH
= V
22
Data
X1h
X0h
68h
68h
60h
IL
RD
RD
RD
(0)
(1)
(0)
—
, A
)
21
, A
SGA+
Addr.
WPE
Fifth Write
WP
PL
—
—
—
—
—
—
—
20
Cycle
, A
19
Data Addr. Data Addr. Data
48h
40h
48h
—
—
—
—
—
—
—
, A
18
, A
Sixth Write
XXh
XXh
XXh
XXh
—
—
—
—
—
—
—
17
Cycle
, A
16
RD
RD
RD
RD
(0)
(0)
(0)
(0)
—
—
—
—
—
—
—
, A
15
(Continued)
, A
Seventh
—
—
—
—
—
—
—
—
—
—
—
Cycle
Write
14
, A
—
—
—
—
—
—
—
—
—
—
—
13
15
,
9