MBM29BS12DH Fujitsu Media Devices, MBM29BS12DH Datasheet - Page 35

• Manufacturer Part Number: MBM29BS12DH
• Description: (MBM29FS12DH / MBM29BS12DH) BURST MODE FLASH MEMORY CMOS 128M (8M X 16) BIT
• Manufacturer: Fujitsu Media Devices

Word Programming Command
Chip Erase Command
verification should be performed by verifying sector group protection on the protected sector. (See “MBM29BS/
FS12DH User Bus Operations Table” in “ DEVICE BUS OPERATIION”. )
The manufacture and device codes can be read from the selected bank. To read the manufacture and device
codes and sector protection status from a non-selected bank, it is necessary to write the Read/Reset command
sequence into the register. Autoselect command should then be written into the bank to be read.
If the software (program code) for Autoselect command is stored in the Flash memory, the device and manu-
facture codes should be read from the other bank, which does not contain the software. No subsequent data
will be made available if the autoselect data is read in synchronous mode.
To terminate the operation, it is necessary to write the Read/Reset command sequence into the register. To
execute the Autoselect command during the operation, Read/Reset command sequence must be written before
the Autoselect command.
The device is programmed on word-by-word basis. Programming is a four bus cycle operation. There are two
“unlock” write cycles. These are followed by the program set-up command and data write cycles. Upon executing
the Embedded Program Algorithm command sequence, the system is not required to provide further controls
or timings. The device will automatically provide adequate internally generated program pulses and verify the
programmed cell margin.
The system can determine the status of the program operation by using DQ
The Data Polling and Toggle Bit must be performed at the memory location which is being programmed.
The automatic programming operation is completed when the data on DQ
bit at which time the device returns to the read mode and addresses are no longer latched (see “Hardware
Sequence Flags Table”). Therefore, the device requires that a valid address to the device be supplied by the
system in this particular instance. Hence, Data Polling must be performed at the memory location which is being
programmed. If hardware reset occurs during the programming operation, the data being written is not guaran-
teed.
Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success
according to the data polling algorithm but a read from Read/Reset mode will show that the data is still “0”. Only
erase operations can convert from “0”s to “1”s.
“Embedded Program
typical command strings and bus operations.
Chip erase is a six-bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.
Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase
Algorithm command sequence the device will automatically program and verify the entire memory for an all zero
data pattern prior to electrical erase. (Preprogram Function). The system is not required to provide any controls
or timings during these operations.
The system can determine the status of the erase operation by using DQ
The chip erase begins on the rising edge of the last WE, whichever happens first in the command sequence
and terminates when the data on DQ
returns to read the mode.
Chip Erase Time; Sector Erase Time
“Embedded Erase
command strings and bus operations.
TM
Algorithm” in “ FLOW CHART” illustrates the Embedded Erase
TM
Algorithm” in “
7
All sectors + Chip Program Time (Preprogramming)
is “1” (See Write Operation Status section. ) at which time the device
FLOW CHART” illustrates the Embedded Program
MBM29BS/FS12DH
7
7
(Data Polling), or DQ
is equivalent to data written to this
7
(Data Polling), DQ
TM
Algorithm using typical
TM
Algorithm using
6
6
(Toggle Bit).
(Toggle Bit).
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