cy28548 SpectraLinear Inc, cy28548 Datasheet - Page 14

• Manufacturer Part Number: cy28548
• Description: Clock Generator For Intel Crestline Chipset
• Manufacturer: SpectraLinear Inc

Rev 1.5 September 16, 2008
is in series with the crystal. The total capacitance on both side
is twice the specified crystal load capacitance (CL). Trim
capacitors are calculated to provide equal capacitive loading
on both sides.
,
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
CL ................................................... Crystal load capacitance
CLe .........................................Actual loading seen by crystal
Ce .....................................................External trim capacitors
Cs ............................................. Stray capacitance (terraced)
Ci .......................................................... Internal capacitance
Dial-A-Frequency
This feature allows the user to over-clock their system by
slowly stepping up the CPU or SRC frequency. When the
programmable output frequency feature is enabled, the CPU
and SRC frequencies are determined by the following
equation:
Fcpu = G * N/M or Fcpu=G2 * N, where G2 = G / M.
• “N” and “M” are the values programmed in Programmable
• “G” stands for the PLL Gear Constant, which is determined
Frequency Select N-Value Register and M-Value Register,
respectively.
by the programmed value of FS[E:A]. See Table 1,
Frequency Select Table for the Gear Constant for each
Frequency selection. The PCI Express only allows user
control of the N register, the M value is fixed and
documented in Table 1, Frequency Select Table.
CLe
C s 1
Total Capacitance (as seen by the crystal)
=
Figure 2. Crystal Loading Example
C e 1
(
Load Capacitance (each side)
Ce1 + Cs1 + Ci1
X 1
C i1
Ce = 2 * CL – (Cs + Ci)
C lo c k C h ip
1
®
X T A L
using standard value trim capacitors
(CPU and PCIEX)
C i2
(lead frame, bond wires, etc.)
+
X 2
1
C e 2
Ce2 + Cs2 + Ci2
C s 2
1
3 to 6 p
3 3 p F
P in
T r im
2 .8 p F
T r a c e
)
In this mode, the user writes the desired N and M values into
the DAF I2C registers. The user cannot change only the M
value and must change both the M and the N values at the
same time, if they require a change to the M value. The user
may change only the N value.
Associated Register Bits
Smooth Switching
The device contains one smooth switch circuit that is shared
by the CPU PLL and SRC PLL. The smooth switch circuit
ensures that when the output frequency changes by
overclocking, the transition from the old frequency to the new
frequency is a slow, smooth transition containing no glitches.
The rate of change of output frequency when using the smooth
switch circuit is less than 1 MHz/0.667 µs. The frequency
overshoot and undershoot is less than 2%.
The Smooth Switch circuit assigns auto or manual. In Auto
mode, clock generator assigns smooth switch automatically
when the PLL does overclocking. For manual mode, assign
the smooth switch circuit to PLL via Smbus. By default the
smooth switch circuit is set to auto mode. PLL can be
over-clocked when it does not have control of the smooth
switch circuit but it is not guaranteed to transition to the new
frequency without large frequency glitches.
Do not enable over-clocking and change the N values of both
PLLs in the same SMBUS block write and use smooth switch
mechanism on spread spectrum on/off.
PD_RESTORE
If a ‘0’ is set for Byte 0 bit 0 then, upon assertion of PWRDWN#
LOW, the CY28548 initiates a full reset. The result of this is
that the clock chip emulates a cold power on start and goes to
the “Latches Open” state. If the PD_RESTORE bit is set to a
‘1’ then the configuration is stored upon PWRDWN# asserted
LOW. Note that if the iAMT bit, Byte 0 bit 3, is set to a ‘1’ then
the PD_RESTORE bit must be ignored. In other words, in Intel
iAMT mode, PWRDWN# reset is not allowed.
• CPU_DAF Enable – This bit enables CPU DAF mode. By
• CPU_DAF_N – There are nine bits (for 512 values) to
• CPU DAF M – There are 7 bits (for 128 values) to linearly
• SRC_DAF Enable – This bit enables SRC DAF mode. By
• SRC_DAF_N – There are nine bits (for 512 values) to
default, it is not set. When set, the operating frequency is
determined by the values entered into the CPU_DAF_N
register. Note that the CPU_DAF_N and M register must
contain valid values before CPU_DAF is set. Default = 0,
(No DAF).
linearly change the CPU frequency (limited by VCO range).
Default = 0, (0000). The allowable values for N are detailed
in Table 1, Frequency Select Table.
change the CPU frequency (limited by VCO range). Default
= 0, the allowable values for M are detailed in Table 1,
Frequency Select Table
default, it is not set. When set, the operating frequency is
determined by the values entered into the SRC_DAF_N
register. Note that the SRC_DAF_N register must contain
valid values before SRC_DAF is set. Default = 0, (No DAF).
linearly change the CPU frequency (limited by VCO range).
Default = 0, (0000). The allowable values for N are detailed
in Table 1, Frequency Select Table.
CY28548
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