cy28548 SpectraLinear Inc, cy28548 Datasheet - Page 2

• Manufacturer Part Number: cy28548
• Description: Clock Generator For Intel Crestline Chipset
• Manufacturer: SpectraLinear Inc

Rev 1.5 September 16, 2008
TSSOP Pin Definitions
Pin No.
1
2
3
4
5
Pin Configuration
PCI0 / CR#_A
VDD_PCI
PCI1 / CR#_B
PCI2 / TME
PCI3
Name
SRCT1/LCDT_100/27M_NSS
SRCC1/LCDC_100/27M_SS
I/O, SE 33 MHz clock/3.3V Clock Request # Input.
I/O, SE 33 MHz Clock/3.3V Clock Request # Input.Selected via CR#_B_EN bit located
I/O, SE 33 MHz clock output / 3.3V-tolerance input for enabling trusted mode
O, SE 33 MHz clock output
PWR 3.3V Power supply for PCI PLL.
Type
PCI4/GCLK_SEL
SRCC0/DOT96C
SRCT0/DOT96T
SRCC2/SATAC
SRCC11/CR#_G
SRCC3/CR#_D
SRCT2/SATAT
SRCT3/CR#_C
VDD_PLL3_IO
PCIF0/ITP_EN
USB_48/FSA
VSS_SRC_IO
PCI0/CR#_A
PCI1/CR#_B
VDD_PLL3
VSS_PLL3
PCI2/TME
VDD_SRC
VSS_SRC
VDD_PCI
VSS_PCI
VDD_48
VDD_IO
VSS_48
VSS_IO
SRCT4
SRCC4
Selected via CR#_A_EN bit located in byte 5 bit 7.
The CR#_A_SEL bit in byte 5 bit 6 will select to control SRC0 or SRC2 when
asserted.
in byte 5 bit 5.
The CR#_B_SEL bit in byte 5 bit 4 will select to control SRC1 or SRC4 when
asserted.
Sampled at CKPWRGD assertion:
0 = Normal mode, 1 = Trusted mode (no overclocking)
SRCC9
SRCT9
PCI3
64-Pin TSSOP
10
1
2
3
4
5
6
7
8
9
11
32
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDD_SRC_IO
SRCC10
SRCT10
SRCT11/CR#_H
SCLK
SDATA
REF0/FSC/TEST_SEL
VDD_REF
XIN
XOUT
VSS_REF
FSB/TEST_MODE
CKPWRGD/PWRDWN#
VDD_CPU
CPUT0
CPUC0
VSS_CPU
CPUC1
VDD_CPU_IO
NC
SRCT8/CPU2_ITPT
SRCC8/CPU2_ITPC
VDD_SRC_IO
SRCT7/CR#_F
SRCC7/CR#_E
VSS_SRC
SRCT6
SRCC6
VDD_SRC
PCI_STOP#
CPU_STOP#
CPUT1
Description
CY28548
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