cy28548 SpectraLinear Inc, cy28548 Datasheet - Page 5

• Manufacturer Part Number: cy28548
• Description: Clock Generator For Intel Crestline Chipset
• Manufacturer: SpectraLinear Inc

Rev 1.5 September 16, 2008
TSSOP Pin Definitions
Table 1. Frequency Select Pin (FSA, FSB and FSC)
Frequency Select Pin (FSA, FSB and FSC)
Apply the appropriate logic levels to FSA, FSB, and FSC
inputs before CK-PWRGD assertion to achieve host clock
frequency selection. When the clock chip sampled HIGH on
CK-PWRGD and indicates that VTT voltage is stable then
FSA, FSB, and FSC input values are sampled. This process
employs a one-shot functionality and once the CK-PWRGD
sampled a valid HIGH, all other FSA, FSB, FSC, and
CK-PWRGD transitions are ignored except in test mode
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers are individually enabled or disabled. The
registers associated with the Serial Data Interface initialize to
their default setting at power-up. The use of this interface is
.
Table 2. Command Code Definition
Pin No.
57
58
59
60
61
62
63
64
(6:0)
FSC
Bit
7
0
0
0
0
1
1
1
1
FSB / TEST_MODE
VSS_REF
Xout
Xin
VDD_REF
REF0 / FSC / TEST_SEL
SDATA
SCLK
0 = Block read or block write operation, 1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
FSB
0
0
1
1
0
0
1
1
Name
FSA
0
1
0
1
0
1
0
1
(continued)
Reserved
266 MHz
133 MHz
200 MHz
166 MHz
333 MHz
100 MHz
400 MHz
O, SE 14.318 MHz Crystal output.
PWR 3.3V Power supply for outputs and also maintains SMBUS registers during
Type
GND
I/O
I/O
CPU
I
I
I
3.3V-tolerant input for CPU frequency selection / Selects Ref/N or Tri-state
when in test mode:
0 = Tri-state, 1 = Ref/N
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
Ground for outputs.
14.318 MHz Crystal input.
power down.
Fixed 14.318 clock output / 3.3V-tolerant input for CPU frequency selection /
Selects test mode if pulled to V
Refer to DC Electrical Specifications table for V
tions.
SMBus-compatible SDATA.
SMBus-compatible SCLOCK.
Reserved
100 MHz
SRC
PCIF/PCI
Reserved
Description
33 MHz
optional. Clock device register changes are normally made at
system initialization, if any are required. The interface cannot
be used during system operation for power management
functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, Access the bytes in sequential
order from lowest to highest (most significant bit first) with the
ability to stop after any complete byte is transferred. For byte
write and byte read operations, the system controller can
access individually indexed bytes. The offset of the indexed
byte is encoded in the command code described in Table 2.
The block write and block read protocol is outlined in Table 3
while Table 4 outlines byte write and byte read protocol. The
slave receiver address is 11010010 (D2h)
Reserved
27 MHz
27MHz
IHFS_C
Description
when CK_PWRGD is asserted HIGH.
14.318 MHz
Reserved
REF
ILFS_C
, V
IMFS_C
Reserved
96 MHz
DOT96
, V
CY28548
IHFS_C
Page 5 of 30
Reserved
48 MHz
specifica-
USB