cy28548 SpectraLinear Inc, cy28548 Datasheet - Page 6

• Manufacturer Part Number: cy28548
• Description: Clock Generator For Intel Crestline Chipset
• Manufacturer: SpectraLinear Inc

Rev 1.5 September 16, 2008
Table 3. Block Read and Block Write Protocol
Table 4. Byte Read and Byte Write Protocol
27:20
36:29
45:38
27:20
18:11
18:11
8:2
8:2
Bit
Bit
10
19
28
37
46
....
....
....
....
10
19
28
29
1
9
1
9
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Byte Count–8 bits
Acknowledge from slave
Data byte 1–8 bits
Acknowledge from slave
Data byte 2–8 bits
Acknowledge from slave
Data Byte /Slave Acknowledges
Data Byte N–8 bits
Acknowledge from slave
Stop
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Data byte–8 bits
Acknowledge from slave
Stop
Block Write Protocol
Byte Write Protocol
Description
Description
27:21
37:30
46:39
55:48
18:11
27:21
18:11
37:30
8:2
Bit
10
19
20
28
29
38
47
56
....
....
....
....
Bit
8:2
10
19
20
28
29
38
39
1
9
1
9
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Repeat start
Slave address–7 bits
Read = 1
Acknowledge from slave
Byte Count from slave–8 bits
Acknowledge
Data byte 1 from slave–8 bits
Acknowledge
Data byte 2 from slave–8 bits
Acknowledge
Data bytes from slave / Acknowledge
Data Byte N from slave–8 bits
NOT Acknowledge
Stop
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Repeated start
Slave address–7 bits
Read
Acknowledge from slave
Data from slave–8 bits
NOT Acknowledge
Stop
Block Read Protocol
Byte Read Protocol
Description
Description
CY28548
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