cy28548 SpectraLinear Inc, cy28548 Datasheet - Page 15

• Manufacturer Part Number: cy28548
• Description: Clock Generator For Intel Crestline Chipset
• Manufacturer: SpectraLinear Inc

Rev 1.5 September 16, 2008
PWRDWN# (Power down) Clarification
The CKPWRGD/PWRDWN# pin is a dual-function pin. During
initial power up, the pin functions as CKPWRGD. Once
CKPWRGD has been sampled HIGH by the clock chip, the pin
assumes PD# functionality. The PD# pin is an asynchronous
active LOW input used to shut off all clocks cleanly before
shutting off power to the device. This signal is synchronized
internally to the device before powering down the clock
synthesizer. PD# is also an asynchronous input for powering
up the system. When PD# is asserted LOW, clocks are driven
to a LOW value and held before turning off the VCOs and the
crystal oscillator.
PWRDWN# (Power down) Assertion
When PD is sampled HIGH by two consecutive rising edges
of CPUC, all single-ended outputs will be held LOW on their
next HIGH-to-LOW transition and differential clocks must held
C P U C , 1 3 3 MH z
C P U T , 1 3 3 MH z
S R C T 1 0 0 MH z
S R C C 1 0 0 MH z
CPUC, 133MHz
CPUT, 133MHz
U S B , 4 8 MH z
SRCC 100MHz
SRCT 100MHz
P C I, 3 3 MH z
PCI, 33 MHz
USB, 48MHz
D OT 9 6 C
D OT 9 6 T
DOT96C
DOT96T
PD#
REF
REF
PD#
Figure 4. Power down Deassertion Timing Waveform
Figure 3. Power down Assertion Timing Waveform
< 3 0 0 µ s , > 2 0 0 m V
Td r iv e _ PW R D N #
Ts ta b le
< 1 .8 m s
LOW. When PD mode is desired as the initial power on state,
PD must be asserted HIGH in less than 10 µs after asserting
CKPWRGD.
PWRDWN# Deassertion
The power up latency is less than 1.8 ms. This is the time from
the deassertion of the PD# pin or the ramping of the power
supply until the time that stable clocks are generated from the
clock chip. All differential outputs stopped in a three-state
condition, resulting from power down are driven high in less
than 300 µs of PD# deassertion to a voltage greater than
200 mV. After the clock chip’s internal PLL is powered up and
locked, all outputs are enabled within a few clock cycles of
each clock. Figure 4 is an example showing the relationship of
clocks coming up.
CY28548
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