cy28548 SpectraLinear Inc, cy28548 Datasheet - Page 18

• Manufacturer Part Number: cy28548
• Description: Clock Generator For Intel Crestline Chipset
• Manufacturer: SpectraLinear Inc

Rev 1.5 September 16, 2008
PCI_STP# Assertion
The PCI_STP# signal is an active LOW input used for
synchronously stopping and starting the PCI outputs while the
rest of the clock generator continues to function. The set-up
time for capturing PCI_STP# going LOW is 10 ns (t
Figure 10.) The PCIF clocks are affected by this pin if their
corresponding control bit in the SMBus register is set to allow
them to be free running.
PCI_STP# Deassertion
The deassertion of the PCI_STP# signal causes all PCI and
stoppable PCIF clocks to resume running in a synchronous
manner within two PCI clock periods, after PCI_STP# transi-
tions to a HIGH level.
CPUC(Free Running)
CPUT(Free Running)
CPUC(Stoppable)
CPUT(Stoppable)
CPU_STOP#
SR C 100 M H z
DOT96T
DOT96C
SR C 100M H z
P C I_S T P #
PC I_STP#
PD#
P C I_F
PC I_F
P C I
PC I
Figure 9. CPU_STP# = Tri-state, CPU_PD = Tri-state, DOT_PD = Tri-state
Figure 11. PCI_STP# Deassertion Waveform
T su
T su
Figure 10. PCI_STP# Assertion Waveform
T drive_ S R C
SU
). (See
.
.
1.8 ms
CY28548
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