cy28548 SpectraLinear Inc, cy28548 Datasheet - Page 3

• Manufacturer Part Number: cy28548
• Description: Clock Generator For Intel Crestline Chipset
• Manufacturer: SpectraLinear Inc

Rev 1.5 September 16, 2008
TSSOP Pin Definitions
Pin No.
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
PCI4 / GCLK_SEL
PCIF0 / ITP_EN
VSS_PCI
VDD_48
USB_48 / FSA
VSS_48
VDD_IO
SRCT0 / DOT96T
SRCC0 / DOT96C
VSS_IO
VDD_PLL3
SRCT1 /
LCDT_100/27M_NSS
SRCC1 /
LCDC_100/27M_SS
VSS_PLL3
VDD_PLL3_IO
SRCT2 / SATAT
SRCC2 / SATAC
VSS_SRC
SRCT3 / CR#_C
SRCC3 / CR#_D
VDD_SRC_IO
SRCT4
SRCC4
VSS_SRC
SRCT9
SRCC9
Name
(continued)
I/O, SE 33 MHz clock output/3.3V-tolerant input for selecting graphic clock source
I/O, SE 33 MHz free running clock output / 3.3V LVTTL input to enable SRC8 or
O, DIF,
O, DIF,
O, DIF True 100 MHz differential serial reference clocks / Fixed True 96 MHz clock
O, DIF Complementary 100 MHz differential serial reference clocks / Fixed Comple-
O, DIF True 100 MHz differential serial reference clock output.
O, DIF Complementary 100 MHz differential serial reference clock output.
O, DIF True 100 MHz differential serial reference clocks.
O, DIF Complementary 100 MHz differential serial reference clocks.
O, DIF True 100 MHz differential serial reference clocks.
O, DIF Complementary 100 MHz differential serial reference clocks.
PWR 3.3V power supply for outputs and PLL.
PWR 3.3V-1.25V power supply for outputs
PWR 3.3V Power supply for PLL3
PWR 3.3V-1.25V power supply for outputs.
PWR 3.3V-1.25V power supply for outputs.
Type
GND
GND
GND
GND
GND
GND
I/O,
DIF
I/O,
DIF
I/O
SE
SE
on pin 13, 14, 17and 18
Sampled on CKPWRGD assertion
CPU2_ITP (sampled on the CKPWRGD assertion)
1 = CPU2_ITP, 0 = SRC8
Ground for outputs.
Fixed 48 MHz clock output / 3.3V-tolerant input for CPU frequency selection
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
Ground for outputs.
output. Selected via GCLK_SEL at CKPWRGD assertion
mentary 96 MHz clock output. Selected via GCLK_SEL at CKPWRGD assertion
Ground for outputs
True 100 MHz differential serial reference clock output / True 100 MHz LCD
video clock output / Non spread 27 MHz video clock output.
Selected via GCLK_SEL at CKPWRGD assertion
Complementary100 MHz differential serial reference clock output / Comple-
mentary 100 MHz LCD video clock output / Spread 27 MHz video clock output.
Selected via GCLK_SEL at CKPWRGD assertion
Ground for PLL3.
Ground for outputs.
True 100 MHz differential serial reference clock output / 3.3V CR #_C/D input
Selected via CR#_C_EN/CR#_D_EN bit located in byte 5 bit 3and 1.
The CR#_C_SEL and CR#_D_SEL bits in byte 5 bit 2 and 0 will select which SRC
to stop when asserted
Complementary 100 MHz differential serial reference clock output / 3.3V CR
#_C/D input
Selected via CR#_C_EN/CR#_D_EN bit located in byte 5 bit 3and 1.
The CR#_C_SEL and CR#_D_SEL bits in byte 5 bit 2 and 0 will select which SRC
to stop when asserted
Ground for outputs.
GCLK_SEL
0
1
DOT96T DOT96C SRC1T/LCD_100T SRC1C/LCD_100C
SRCT0
Pin13
SRCC0
Pin14
Description
27M_NSS
Pin17
27M_SS
Pin 18
CY28548
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