upd44645182af5-fq1-a Renesas Electronics Corporation., upd44645182af5-fq1-a Datasheet
upd44645182af5-fq1-a
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upd44645182af5-fq1-a Summary of contents
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PD44645092A-A, 44645182A-A, 44645362A-A Description μ The PD44645092A 8,388,608-word by 9-bit, the μ PD44645362A 2,097,152-word by 36-bit synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. μ μ ...
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Ordering Information Part number Cycle Time ns μ PD44645092AF5-E33-FQ1-A 3.3 μ PD44645092AF5-E40-FQ1-A 4.0 μ PD44645092AF5-E50-FQ1-A 5.0 μ PD44645182AF5-E33-FQ1-A 3.3 μ PD44645182AF5-E40-FQ1-A 4.0 μ PD44645182AF5-E50-FQ1-A 5.0 μ PD44645362AF5-E33-FQ1-A 3.3 μ PD44645362AF5-E40-FQ1-A 4.0 μ PD44645362AF5-E50-FQ1-A 5.0 Remark Products with -A at the ...
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Pin Configurations CQ DLL ...
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A CQ /144M D10 D NC D11 Q10 Q11 Q12 D12 D13 Q13 V H DLL ...
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A CQ /288M SS B Q27 Q18 D18 C D27 Q28 D19 D D28 D20 Q19 E Q29 D29 Q20 V F Q30 Q21 D21 V G D30 D22 Q22 V H DLL ...
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Pin Identification Symbol Type A Input Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the rising edge of K for READ cycles and must meet the setup and hold times around the ...
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Symbol Type CQ, CQ# Output Synchronous Echo Clock Outputs. The rising edges of these outputs are tightly matched to the synchronous data outputs and can be used as a data valid indication. These signals run freely and do not stop ...
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Block Diagram μ [ PD44645092A-A] 22 ADDRESS R# ADDRESS W# REGISTRY & LOGIC BW0# DATA 18 9 REGISTRY & LOGIC μ [ PD44645182A-A] 21 ADDRESS R# ADDRESS W# REGISTRY & ...
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PD44645362A-A] 20 ADDRESS R# ADDRESS W# REGISTRY & LOGIC BW0# BW1# BW2# DATA 72 BW3# REGISTRY D35 & LOGIC μ PD44645092A-A, 44645182A-A, 44645362A ...
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Power-On Sequence in QDR II SRAM QDR II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. The following timing charts show the recommended power-on sequence. The following power-up supply voltage application is recommended: ...
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Truth Table Operation CLK L → H WRITE cycle Load address, input write data on consecutive K and K# rising edge READ cycle L → H Load address, output data on consecutive C and C# rising edge L → H ...
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Byte Write Operation μ [ PD44645092A-A] Operation K Write → H − Write nothing L → H − Remarks HIGH LOW, → : rising edge. 2. Assumes a WRITE cycle was ...
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Bus Cycle State Diagram LOAD NEW WRITE ADDRESS AT K# Always W# = LOW WRITE DOUBLE LOW W# = HIGH W# = HIGH WRITE PORT NOP Remarks 1. The address is concatenated with 1 additional internal ...
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Electrical Specifications Absolute Maximum Ratings Parameter Symbol Supply voltage V Output supply voltage V Input voltage Input / Output voltage Operating ambient temperature Storage temperature Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause ...
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DC Characteristics ( 70° Parameter Symbol Input leakage current I LI I/O leakage current I LO Operating supply current I V ≤ (Read cycle / Write cycle mA, ...
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AC Characteristics ( 70° Test Conditions (V = 1.8 ± 0 Input waveform (Rise / Fall time ≤ 0.3 ns) 1.25 V 0.75 V 0.25 V Output waveform V Q ...
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Read and Write Cycle Parameter Clock Average Clock cycle time (K, K#, C, C#) Clock phase jitter (K, K#, C, C#) Clock HIGH time (K, K#, C, C#) Clock LOW time (K, K#, C, C#) Clock HIGH to Clock# HIGH ...
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Notes 1. When debugging the system or board, these products can operate at a clock frequency slower than TKHKH (MAX.) without the DLL/PLL circuit being used, if DLL# = LOW. Read latency (RL) is changed to 1.0 clock cycle in ...
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Read and Write Timing READ WRITE TKHKL TKLKH K# R# TIVKH Address TAVKH TKHAX TAVKH D10 D11 Data in Data out CQ CQ# TKHCH C TKHKL C# Remarks 1. Q00 refers to output from ...
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Application Example SRAM BWx# C/C# K/ SRAM Controller R Data In Data Out Address R# W# BW# SRAM#1 CQ/CQ SRAM#4 CQ/CQ Source CLK/CLK# Return CLK/CLK ...
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JTAG Specification These products support a limited set of JTAG functions as in IEEE standard 1149.1. Test Access Port (TAP) Pins Pin name Pin assignments Test Clock Input. All input are captured on the rising edge of TCK and all ...
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JTAG AC Test Conditions Input waveform (Rise / Fall time ≤ 1 ns) 1 Output waveform 0.9 V Output load 22 μ PD44645092A-A, 44645182A-A, 44645362A-A Test Points Test Points Figure 2. External load at test ...
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JTAG AC Characteristics ( 70°C) A Parameter Symbol Clock Clock cycle time t THTH Clock frequency f TF Clock HIGH time t THTL Clock LOW time t TLTH Output time TCK LOW to TDO unknown t TLOX ...
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Scan Register Definition (1) Register name Instruction register The instruction register holds the instructions that are executed by the TAP controller when it is moved into the run-test/idle or the various data register state. The register can be loaded when ...
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SCAN Exit Order Bit Signal name Bump no. x9 x18 x36 ...
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JTAG Instructions Instructions EXTEST The EXTEST instruction allows circuitry external to the component package to be tested. Boundary- scan register cells at output pins are used to apply test vectors, while those at input pins capture test results. Typically, the ...
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Output Pin States of CQ, CQ# and Q Instructions Control-Register Status EXTEST 0 1 IDCODE 0 1 SAMPLE SAMPLE 0 1 BYPASS 0 1 Remark The output pin statuses during each instruction vary according to the Control-Register status ...
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Boundary Scan Register Status of Output Pins CQ, CQ# and Q Instructions SRAM Status EXTEST READ (Low-Z) NOP (High-Z) IDCODE READ (Low-Z) NOP (High-Z) SAMPLE-Z READ (Low-Z) NOP (High-Z) SAMPLE READ (Low-Z) NOP (High-Z) BYPASS READ (Low-Z) NOP (High-Z) Remark ...
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TAP Controller State Diagram 1 Test-Logic-Reset Run-Test / Idle Disabling the Test Access Port It is possible to use this device without utilizing the TAP. To disable the TAP Controller without interfering with normal operation of the ...
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PD44645092A-A, 44645182A-A, 44645362A-A Run-Test/Idle Update-IR Exit1-IR Shift-IR Exit2-IR Pause-IR Exit1-IR Shift-IR Capture-IR Select-IR-Scan Select-DR-Scan Run-Test/Idle Test-Logic-Reset Preliminary Data Sheet M19958EJ1V0DS ...
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PD44645092A-A, 44645182A-A, 44645362A-A Test-Logic-Reset Select-IR-Scan Select-DR-Scan Run-Test/Idle Update-DR Exit1-DR Shift-DR Exit2-DR Pause-DR Exit1-DR Shift-DR Capture-DR Select-DR-Scan Run-Test/Idle Preliminary Data Sheet M19958EJ1V0DS 31 ...
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Package Drawing 165-PIN PLASTIC BGA(15x17) E INDEX MARK μ PD44645092A-A, 44645182A-A, 44645362A ...
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Recommended Soldering Condition Please consult with our sales offices for soldering conditions of these products. Types of Surface Mount Devices μ PD44645092AF5-FQ1-A : 165-pin PLASTIC BGA (15 x 17) μ PD44645182AF5-FQ1-A : 165-pin PLASTIC BGA (15 x 17) μ PD44645362AF5-FQ1-A ...
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PD44645092A-A, 44645182A-A, 44645362A-A Preliminary Data Sheet M19958EJ1V0DS ...
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NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V malfunction. Take care ...
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QDR RAMs and Quad Data Rate RAMs comprise a new series of products developed by Cypress Semiconductor, Renesas, IDT, NEC Electronics, and Samsung. • The information in this document is current as of August, 2009. The information is subject to ...