upd44645182af5-fq1-a Renesas Electronics Corporation., upd44645182af5-fq1-a Datasheet - Page 10

• Manufacturer Part Number: upd44645182af5-fq1-a
• Description: 72m-bit Qdrtm Ii Sram 2-word Burst Operation
• Manufacturer: Renesas Electronics Corporation.

Power-On Sequence in QDR II SRAM
10
can be applied simultaneously, as long as V
following power-down supply voltage removal sequence is recommended: V
can be removed simultaneously, as long as V
The following timing charts show the recommended power-on sequence.
V
DD
QDR II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
The following power-up supply voltage application is recommended: V
Power-On Sequence
DLL/PLL Constraints
Power-On Waveforms
/V
Apply power and tie DLL# to HIGH.
Provide stable clock for more than 20
The DLL/PLL uses K clock as its synchronizing input and the input should have low phase jitter which is specified
as TKC var. The DLL/PLL can cover 120 MHz as the lowest frequency. If the input clock is unstable and the
DLL/PLL is enabled, then the DLL/PLL may lock onto an undesired clock frequency.
DLL#
Clock
- Apply V
- Apply V
DD
Q
DD
DD
Q before V
before V
Unstable Clock
DD
REF
Q.
or at the same time as V
V
DD
Preliminary Data Sheet M19958EJ1V0DS
μ
/V
s to lock the DLL/PLL.
DD
DD
Q Stable (< ±0.1 V DC per 50 ns)
DD
Q does not exceed V
Q does not exceed V
μ
PD44645092A-A, 44645182A-A, 44645362A-A
REF.
Fix HIGH (or tied to V
20 μs or more
Stable Clock
DD
DD
by more than 0.5 V during power-up. The
by more than 0.5 V during power-down.
SS
, V
DD
IN
Q)
DD
, V
, V
REF
DD
, V
Q, V
DD
REF
Q, V
, then V
DD
, V
SS
IN
. V
Normal Operation
Start
. V
DD
DD
and V
and V
DD
DD
Q
Q