upd44645182af5-fq1-a Renesas Electronics Corporation., upd44645182af5-fq1-a Datasheet - Page 18

• Manufacturer Part Number: upd44645182af5-fq1-a
• Description: 72m-bit Qdrtm Ii Sram 2-word Burst Operation
• Manufacturer: Renesas Electronics Corporation.

Notes 1. When debugging the system or board, these products can operate at a clock frequency slower than TKHKH
Remarks 1. This parameter is sampled.
18
4. K input is monitored for this operation. See below for the timing.
2. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. TKC var
3. V
5. Guaranteed by design.
6. Echo clock is very tightly controlled to data valid / data hold. By design, there is a ± 0.1 ns variation from
7. This is a synchronous device. All addresses, data and control lines must meet the specified setup
(MAX.) without the DLL/PLL circuit being used, if DLL# = LOW. Read latency (RL) is changed to 1.0 clock
cycle in this operation. The AC/DC characteristics cannot be guaranteed, however.
DLL/PLL lock time begins once V
It is recommended that the device is kept NOP (R# = W# = HIGH) during these cycles.
K
2. Test conditions as specified with the output loading as shown in AC Test Conditions unless otherwise
3. Control input signals may not be operated with pulse widths less than TKHKL (MIN.).
4. If C, C# are tied HIGH, K, K# become the references for C, C# timing parameters.
5. V
or
K
echo clock to data. The data sheet parameters reflect tester guardbands and test setup variations.
(MAX.) indicates a peak-to-peak value.
and hold times for all latching clock edges.
DD
noted.
slew rate must be less than 0.1 V DC per 50 ns for DLL/PLL lock retention.
DD
Q is 1.5 V DC.
TKC reset
TKC reset
Preliminary Data Sheet M19958EJ1V0DS
DD
and input clock are stable.
μ
PD44645092A-A, 44645182A-A, 44645362A-A