upd44645182af5-fq1-a Renesas Electronics Corporation., upd44645182af5-fq1-a Datasheet - Page 7
upd44645182af5-fq1-a
Manufacturer Part Number
upd44645182af5-fq1-a
Description
72m-bit Qdrtm Ii Sram 2-word Burst Operation
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD44645182AF5-FQ1-A.pdf
(36 pages)
CQ, CQ#
ZQ
DLL#
TMS
TDI
TCK
TDO
V
V
V
V
NC
REF
DD
DD
SS
Symbol
Q
Output
Input
Input
Input
Input
Output
−
Supply
Supply
Supply
−
Type
Synchronous Echo Clock Outputs. The rising edges of these outputs are tightly matched to the
synchronous data outputs and can be used as a data valid indication. These signals run freely
and do not stop when Q tristates. If C and C# are stopped (if K and K# are stopped in the single
clock mode), CQ and CQ# will also stop.
Output Impedance Matching Input: This input is used to tune the device outputs to the system
data bus impedance. Q, CQ and CQ# output impedance are set to 0.2 x RQ, where RQ is a
resistor from this bump to ground. The output impedance can be minimized by directly connect
ZQ to V
impedance is adjusted every 20
temperature. After replacement for a resistor, the new output impedance is reset by implementing
power-on sequence.
DLL/PLL Disable: When debugging the system or board, the operation can be performed at a
clock frequency slower than TKHKH (MAX.) without the DLL/PLL circuit being used, if DLL# =
LOW. The AC/DC characteristics cannot be guaranteed. For normal operation, DLL# must be
HIGH and it can be connected to V
IEEE 1149.1 Test Inputs: 1.8 V I/O level. These balls may be left Not Connected if the JTAG
function is not used in the circuit.
IEEE 1149.1 Clock Input: 1.8 V I/O level. This pin must be tied to V
used in the circuit.
IEEE 1149.1 Test Output: 1.8 V I/O level.
When providing any external voltage to TDO signal, it is recommended to pull up to V
HSTL Input Reference Voltage: Nominally V
buffers.
Power Supply: 1.8 V nominal. See Recommended DC Operating Conditions and DC
Characteristics for range.
Power Supply: Isolated Output Buffer Supply. Nominally 1.5 V. 1.8 V is also permissible. See
Recommended DC Operating Conditions and DC Characteristics for range.
Power Supply: Ground
No Connect: These signals are not connected internally.
DD
Q. This pin cannot be connected directly to GND or left unconnected. The output
Preliminary Data Sheet M19958EJ1V0DS
μ
PD44645092A-A, 44645182A-A, 44645362A-A
μ
DD
s upon power-up to account for drifts in supply voltage and
Q through a 10 kΩ or less resistor.
Description
DD
Q/2. Provides a reference voltage for the input
SS
if the JTAG function is not
DD
.
(2/2)
7