upd44645182af5-fq1-a Renesas Electronics Corporation., upd44645182af5-fq1-a Datasheet - Page 21

• Manufacturer Part Number: upd44645182af5-fq1-a
• Description: 72m-bit Qdrtm Ii Sram 2-word Burst Operation
• Manufacturer: Renesas Electronics Corporation.

JTAG Specification
These products support a limited set of JTAG functions as in IEEE standard 1149.1.
Test Access Port (TAP) Pins
Remark The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held HIGH
JTAG DC Characteristics (T
JTAG Input leakage current
JTAG I/O leakage current
TCK
TMS
TDI
TDO
JTAG input HIGH voltage
JTAG input LOW voltage
JTAG output HIGH voltage
JTAG output LOW voltage
Pin name
Parameter
for five rising edges of TCK. The TAP controller state is also reset on the SRAM POWER-UP.
2R
10R
11R
1R
Pin assignments
A
Symbol
= 0 to 70°C, V
V
V
V
V
V
I
V
I
OH1
OH2
LO
OL1
OL2
LI
IH
IL
Test Clock Input. All input are captured on the rising edge of TCK and all outputs
propagate from the falling edge of TCK.
Test Mode Select. This is the command input for the TAP controller state machine.
Test Data Input. This is the input side of the serial registers placed between TDI and
TDO. The register placed between TDI and TDO is determined by the state of the TAP
controller state machine and the instruction that is currently loaded in the TAP instruction.
Test Data Output. This is the output side of the serial registers placed between TDI and
TDO. Output changes in response to the falling edge of TCK.
0 V ≤ V
0 V ≤ V
Outputs disabled
| I
| I
I
I
OLC
OLT
OHC
OHT
Preliminary Data Sheet M19958EJ1V0DS
= 2 mA
= 100
DD
| = 100
| = 2 mA
IN
IN
= 1.8 ± 0.1 V, unless otherwise noted)
≤ V
≤ V
Conditions
μ
μ
A
DD
DD
PD44645092A-A, 44645182A-A, 44645362A-A
μ
Q ,
A
Description
MIN.
−
−
−
1.3
1.6
1.4
5.0
5.0
0.3
V
MAX.
DD
+5.0
+5.0
+0.5
0.2
0.4
+0.3
Unit
μ
μ
V
V
V
V
V
V
A
A
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