upd78f0124hgba1-8et-a Renesas Electronics Corporation., upd78f0124hgba1-8et-a Datasheet - Page 126

• Manufacturer Part Number: upd78f0124hgba1-8et-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

(3) 16-bit timer capture/compare register 010 (CR010)
Remarks 1. Setting ES001, ES000 = 1, 0 is prohibited.
126
Falling edge
Rising edge
Both rising and falling edges
CR010 is a 16-bit register that has the functions of both a capture register and a compare register. Whether it is
used as a capture register or a compare register is set by bit 2 (CRC002) of capture/compare control register 00
(CRC00).
CR010 can be set by a 16-bit memory manipulation instruction.
RESET input clears CR010 to 0000H.
• When CR010 is used as a compare register
• When CR010 is used as a capture register
Cautions 1. If CR010 is cleared to 0000H, an interrupt request (INTTM010) is generated when the value of
The value set in the CR010 is constantly compared with the 16-bit timer counter 00 (TM00) count value, and
an interrupt request (INTTM010) is generated if they match. The set value is held until CR010 is rewritten.
It is possible to select the valid edge of the TI000 pin as the capture trigger. The valid edge of the TI000 pin is
set by prescaler mode register 00 (PRM00) (see Table 6-3).
CR010 Capture Trigger
2. ES001, ES000: Bits 5 and 4 of prescaler mode register 00 (PRM00)
Address: FF14H, FF15H
Symbol
CR010
CRC002:
2. When CR010 is used as a capture register, read data is undefined if the register read time
3. CR010 can be rewritten during TM00 operation. For details, see Caution 2 in Figure 6-15.
Table 6-3. CR010 Capture Trigger and Valid Edge of TI000 Pin (CRC002 = 1)
CR010 changes from 0000H to 0001H following TM00 overflow (FFFFH).
INTTM010 is generated after a match of TM00 and CR010 is detected, a valid edge of the
TI000 pin is detected, and the timer is cleared by a one-shot trigger.
and capture trigger input conflict (the capture data itself is the correct value).
If count stop input and capture trigger input conflict, the captured data is undefined.
Figure 6-4. Format of 16-Bit Timer Capture/Compare Register 010 (CR010)
Bit 2 of capture/compare control register 00 (CRC00)
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
FF15H
After reset: 0000H
Falling edge
Rising edge
Both rising and falling edges
User’s Manual U16962EJ3V0UD
R/W
TI000 Pin Valid Edge
FF14H
ES001
0
0
1
ES000
Moreover,
0
1
1