upd78f0124hgba1-8et-a Renesas Electronics Corporation., upd78f0124hgba1-8et-a Datasheet - Page 422

• Manufacturer Part Number: upd78f0124hgba1-8et-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

422
Call/return
Stack
manipulate
Unconditional
branch
Conditional
branch
Instruction
Notes 1.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
Group
2.
CALL
CALLF
CALLT
BRK
RET
RETI
RETB
PUSH
POP
MOVW
BR
BC
BNC
BZ
BNZ
Mnemonic
2. This clock cycle applies to the internal ROM program.
When the internal high-speed RAM area is accessed or for an instruction with no data access
When an area except the internal high-speed RAM area is accessed
control register (PCC).
!addr16
!addr11
[addr5]
PSW
rp
PSW
rp
SP, #word
SP, AX
AX, SP
!addr16
$addr16
AX
$addr16
$addr16
$addr16
$addr16
Operands
CHAPTER 26 INSTRUCTION SET
User’s Manual U16962EJ3V0UD
Bytes
3
2
1
1
1
1
1
1
1
1
1
4
2
2
3
2
2
2
2
2
2
Note 1
7
5
6
6
6
6
6
2
4
2
4
−
−
−
6
6
8
6
6
6
6
Clocks
Note 2
10
−
−
−
−
−
−
−
−
−
−
−
8
8
−
−
−
−
−
−
−
(SP − 1) ← (PC + 3)
PC ← addr16, SP ← SP − 2
(SP − 1) ← (PC + 2)
PC
SP ← SP − 2
(SP − 1) ← (PC + 1)
PC
PC
SP ← SP − 2
(SP − 1) ← PSW, (SP − 2) ← (PC + 1)
(SP − 3) ← (PC + 1)
PC
PC
SP ← SP + 2
PC
PSW ← (SP + 2), SP ← SP + 3
PC
PSW ← (SP + 2), SP ← SP + 3
(SP − 1) ← PSW, SP ← SP − 1
(SP − 1) ← rp
SP ← SP − 2
PSW ← (SP), SP ← SP + 1
rp
SP ← SP + 2
SP ← word
SP ← AX
AX ← SP
PC ← addr16
PC ← PC + 2 + jdisp8
PCH ← A, PC
PC ← PC + 2 + jdisp8 if CY = 1
PC ← PC + 2 + jdisp8 if CY = 0
PC ← PC + 2 + jdisp8 if Z = 1
PC ← PC + 2 + jdisp8 if Z = 0
H
15 − 11
H
L
L
H
H
H
← (SP + 1), rp
← (00000000, addr5),
← (003EH), SP ← SP − 3, IE ← 0
← (00000000, addr5 + 1),
← (SP + 1), PC
← (SP + 1), PC
← (SP + 1), PC
← 00001, PC
CPU
H
L
, (SP − 2) ← rp
← X
) selected by the processor clock
Operation
L
← (SP),
H
H
H
L
L
L
L
, PC
, (SP − 2) ← (PC + 3)
, (SP − 2) ← (PC + 2)
, (SP − 2) ← (PC + 1)
← (SP),
← (SP),
← (SP),
10 − 0
H
← addr11,
← (003FH),
L
,
H
,
L
L
L
,
,
,
R R R
R R R
R R R
Z AC CY
Flag