upd78f0124hgba1-8et-a Renesas Electronics Corporation., upd78f0124hgba1-8et-a Datasheet - Page 486

• Manufacturer Part Number: upd78f0124hgba1-8et-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

486
8-bit
timers H0,
H1
(TMH0,
TMH1)
Watch
timer
Watchdog
timer
Function
PWM output
Carrier
generator mode
(TMH1 only)
WTM: Watch
timer operation
mode register
Interrupt
request
WDTM:
Watchdog timer
mode register
Details of
Function
In PWM output mode, three operation clocks (signal selected using the CKSn2 to
CKSn0 bits of the TMHMDn register) are required to transfer the CMP1n register
value after rewriting the register.
Be sure to set the CMP1n register when starting the timer count operation
(TMHEn = 1) after the timer count operation was stopped (TMHEn = 0) (be sure
to set again even if setting the same value to the CMP1n register).
Make sure that the CMP1n register setting value (M) and CMP0n register setting
value (N) are within the following range.
00H ≤ CMP1n (M) < CMP0n (N) ≤ FFH
Do not rewrite the NRZB1 bit again until at least the second clock after it has
been rewritten, or else the transfer from the NRZB1 bit to the NRZ1 bit is not
guaranteed.
When 8-bit timer/event counter 51 is used in the carrier generator mode, an
interrupt is generated at the timing of <1>. When 8-bit timer/event counter 51 is
used in a mode other than the carrier generator mode, the timing of the interrupt
generation differs.
Be sure to set the CMP11 register when starting the timer count operation
(TMHE1 = 1) after the timer count operation was stopped (TMHE1 = 0) (be sure
to set again even if setting the same value to the CMP11 register).
Set so that the count clock frequency of TMH1 becomes more than 6 times the
count clock frequency of TM51.
Set the values of the CMP01 and CMP11 registers in a range of 01H to FFH.
In the carrier generator mode, three operating clocks (signal selected by CKS12
to CKS10 bits of TMHMD1 register) or more are required from when the CMP11
register value is changed to when the value is transferred to the register.
Be sure to set the RMC1 bit before the count operation is started.
Do not change the count clock and interval time (by setting bits 4 to 7 (WTM4 to
WTM7) of WTM) during watch timer operation.
When operation of the watch timer and 5-bit counter is enabled by the watch
timer mode control register (WTM) (by setting bits 0 (WTM0) and 1 (WTM1) of
WTM to 1), the interval until the first interrupt request (INTWT) is generated after
the register is set does not exactly match the specification made with bits 2 and 3
(WTM2 and WTM3) of WTM. Subsequently, however, the INTWT signal is
generated at the specified intervals.
If data is written to WDTM, a wait cycle is generated. Do not write data to WDTM
when the CPU is operating on the subsystem clock and the high-speed system
clock is stopped. For details, see CHAPTER 31 CAUTIONS FOR WAIT.
Set bits 7, 6, and 5 to 0, 1, and 1, respectively (when “internal oscillator cannot be
stopped” is selected by the option byte, other values are ignored).
After reset is released, WDTM can be written only once by an 8-bit memory
manipulation instruction. If writing attempted a second time, an internal reset
signal is generated. If the source clock to the watchdog timer is stopped,
however, an internal reset signal is generated when the source clock to the
watchdog timer resumes operation.
APPENDIX D LIST OF CAUTIONS
User’s Manual U16962EJ3V0UD
Cautions
p. 192
p. 192
p. 193
p. 198
p. 198
p. 200
p. 200
p. 200
p. 200
p. 200
p. 207
p. 210
p. 215
p. 215
p. 215
Page
(10/23)