si3200-x-gs Silicon Laboratories, si3200-x-gs Datasheet - Page 68

• Manufacturer Part Number: si3200-x-gs
• Description: Dual Programmable Cmos Slic With Line Monitoring
• Manufacturer: Silicon Laboratories

Si3232
IRQ0: Interrupt Status 0 (Register Address 14)
(Register type: Operational/single value instance for both channels)
Reset settings = 0x00
Read this interrupt to indicate which interrupt status byte, from which channel, has a pending interrupt.
68
Name
Type
Bit
Bit
7
6
5
4
3
2
1
0
CLKIRQ
Reserved
CLKIRQ
IRQ3B
IRQ2B
IRQ1B
IRQ3A
IRQ2A
IRQ1A
Name
D7
R
IRQ3B
D6
R
Clock Failure Interrupt Pending.
0 = No interrupt pending.
1 = Clock failure interrupt pending. Clock failure status indicated in MSTRSTAT register,
bits 7:5.
Interrupt Pending.
0 = No interrupt pending.
1 = Interrupt pending in interrupt status byte 3 (IRQ3) for channel B.
Interrupt Pending.
0 = No interrupt pending.
1 = Interrupt pending in interrupt status byte 2 (IRQ2) for channel B.
Interrupt Pending.
0 = No interrupt pending.
1 = Interrupt pending in interrupt status byte 1 (IRQ1) for channel B.
Read returns zero.
Interrupt Pending.
0 = No interrupt pending.
1 = Interrupt pending in interrupt status byte 3 (IRQ3) for channel A.
Interrupt Pending.
0 = No interrupt pending.
1 = Interrupt pending in interrupt status byte 2 (IRQ2) for channel A.
Interrupt Pending.
0 = No interrupt pending.
1 = Interrupt pending in interrupt status byte 1 (IRQ1) for channel A.
IRQ2B
D5
R
IRQ1B
Preliminary Rev. 0.96
D4
R
D3
Function
IRQ3A
D2
R
IRQ2A
D1
R
IRQ1A
D0
R