si3200-x-gs Silicon Laboratories, si3200-x-gs Datasheet - Page 77

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si3200-x-gs

Manufacturer Part Number
si3200-x-gs
Description
Dual Programmable Cmos Slic With Line Monitoring
Manufacturer
Silicon Laboratories
Datasheet
MSTREN: Master Initialization Enable (Register Address 2)
(Register type: Initialization/single value instance for both channels)
Reset settings = 0x00
Name
Type
Bit
4:0
Bit
7
6
5
PLLFLT
Reserved
PLLFLT
R/W
PCFLT
FSFLT
Name
D7
FSFLT
R/W
D6
PLL Lock Fault Enable.
0 = PLLFAULT interrupt bit is enabled.
1 = PLLFAULT interrupt bit is disabled.
FSYNC Clock Fault Enable.
0 = FSYNC interrupt bit is enabled.
1 = FSYNC interrupt bit is disabled.
PCM Clock Fault Enable.
0 = PCM interrupt bit is enabled.
1 = PCM interrupt bit is disabled.
Read returns zero.
PCFLT
R/W
D5
Preliminary Rev. 0.96
D4
D3
Function
D2
D1
D0
Si3232
77

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