fs6131 AMI Semiconductor, Inc., fs6131 Datasheet - Page 25

• Manufacturer Part Number: fs6131
• Description: Fs6131-01g Programmable Line Lock Clock Generator Ic
• Manufacturer: AMI Semiconductor, Inc.

FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC
Table 15: AC Specifications (Continued)
Unless otherwise stated, V
nominal characterization data at T
Table 16: Serial Interface Timing Specifications
Unless otherwise stated, V
nominal characterization data and are not production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical.
Parameter
Divider Modulus
Clock Output (CLKP, CLKN)
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www.amis.com
Feedback Divider
Reference Divider
Post Divider
Duty Cycle *
Jitter, Long Term (σ
Jitter, Period (peak-peak)
*
Parameter
Clock frequency
Bus free time between STOP and START
Set up time, START (repeated)
Hold time, START
Set up time, data input
Hold time, data input
Output data valid from clock
Rise time, data and clock
Fall time, data and clock
High time, clock
Low time, clock
Set up time, STOP
Specifications subject to change without notice
y
DD
DD
– Rev. 3.0, Jan. 08
(τ)) *
= 5.0V ± 10%, no load on any output, and ambient temperature range T
= 5.0V ± 10%, no load on any output, and ambient temperature range T
A
= 27°C and are not production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical.
Symbol
N
N
N
N
N
t
t
j(LT)
j(∆P)
P1
P2
P3
F
R
Conditions/Description
FBKDIV[13:0] (See also Table 2)
REFDIV[11:0]
POST1[1:0] (See also Table 8)
POST2[1:0] (See also Table 8)
POST3[1:0] (See also Table 8)
Ratio of pulse width (as measured from rising edge to next falling
edge at 2.5V) to one clock period
Rising edges 50ms apart at 2.5V, relative to an ideal clock,
C
R
Rising edges 50ms apart at 2.5V, relative to an ideal clock,
C
R
On rising edges 5ms apart at 2.5V relative to an ideal clock,
C
R
On rising edges 500µs apart at 2.5V relative to an ideal clock,
C
On rising edges 500µs apart at 2.5V relative to an ideal clock,
C
From rising edge to next rising edge at 2.5V, C
f
C
From rising edge to next rising edge at 2.5V, C
f
C
From rising edge to next rising edge at 2.5V, C
f
C
From rising edge to next rising edge at 2.5V, C
CMOS mode, f
From rising edge to next rising edge at 2.5V, C
PECL mode, f
REF
REF
REF
L
LF
L
LF
L
LF
L
L
LP
LP
LP
=15pF, f
=15pF, f
=15pF, f
=15pF, CMOS mode, f
=15pF, PECL mode, f
=15.7kΩ, C
=15.7kΩ, C
=15.7kΩ, C
=8kHz, N
=1800pF, OSCTYPE=0, MLCP=3, XLROM=7
=15kHz, N
=820pF, OSCTYPE=0, MLCP=3, XLROM=7
=31.5kHz, N
=470pF, OSCTYPE=0, MLCP=3, XLROM=7
Symbol
t
t
t
t
t
su:STA
hd:STA
su:DAT
hd:DAT
su:STO
f
t
t
t
SCL
BUF
t
t
t
AA
LO
HI
R
F
REF
REF
REF
R
=8kHz, N
=15kHz, N
=31.5kHz, N
=1, N
XIN
R
LP
LP
LP
XIN
=1, N
R
=1800pF, OSCTYPE=0, MLCP=3, XLROM=7
=820pF, OSCTYPE=0, MLCP=3, XLROM=7
=470pF, OSCTYPE=0, MLCP=3, XLROM=7
=27MHz, N
=1, N
=27MHz, N
F
Conditions/Description
SCL
SDA
SDA
Minimum delay to bridge undefined region of the falling
edge of SCL to avoid unintended START or STOP
SDA, SCL
SDA, SCL
SCL
SCL
=193, N
F
=800, N
F
R
=799, N
=1, N
XIN
R
XIN
=1, N
R
=27MHz, N
=1, N
=27MHz, N
F
Px
F
=200, N
F
Px
=200, N
=64, C
=193, N
F
=10, C
Px
=800, N
F
=4, C
=799, N
25
LF
R
R
F
=27, N
LF
Px
=0.054µF, R
LF
=27, N
F
=200, N
Px
=200, N
=0.0246µF, R
=64, C
=0.015µF, R
=10, C
Px
=4, C
Px
Px
=1
L
L
L
L
L
LF
R
=2
=15pF,
=15pF,
=15pF,
=15pF,
=15pF,
R
=27, N
LF
=0.054µF,
LF
=27, N
=0.0246µF,
=0.015µF,
LF
=15.7kΩ,
LF
LF
Px
=15.7kΩ,
=15.7kΩ,
Px
=1
=2
A
A
= 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent
= 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent
25.175
25.175
1.544
12.00
1.544
12.00
Clock
(MHz)
100
100
200
100
200
Min.
250
4.7
4.7
4.0
4.0
4.7
4.0
Min.
0
0
47
8
1
1
1
1
Typ.
270
160
100
140
130
105
340
270
30
30
Max.
1000
400
300
3.5
16383
Max.
4095
54
8
5
5
Units
kHz
µs
µs
µs
ns
µs
µs
ns
ns
µs
µs
µs
Data Sheet
Units
ps
ps
%