fs6131 AMI Semiconductor, Inc., fs6131 Datasheet - Page 35

• Manufacturer Part Number: fs6131
• Description: Fs6131-01g Programmable Line Lock Clock Generator Ic
• Manufacturer: AMI Semiconductor, Inc.

FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC
12.0 Device Application: Stand-Alone Clock Generation
The length of the reference and feedback dividers, their granularity and the flexibility of the post divider make the FS6131 the most
flexible monolithic stand-alone PLL clock generation device available. The effective block diagram of the FS6131 when programmed for
stand-alone mode is shown in Figure 25.
The source of the feedback divider in the stand-alone mode is the output of the VCO. By dividing the input reference frequency down by
reference divider (N
frequency by the post divider (N
can be written as
where the reference source frequency (f
Great flexibility is permitted in the programming of the FS6131 to achieve exact desired output frequencies since three integers are
involved in the computation.
12.1 Example Calculation
A Visual BASIC program is available to completely program the FS6131 based on the given parameters.
Suppose that the reference source frequency is 14.318MHz and the desired output frequency is 100MHz.
First, factor the 14.318MHz reference frequency (which is four times the NTSC television color sub-carrier) into prime numbers. The
exact expression is
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(optional)
XOUT
REF
FBK
SCL
SDA
XTUNE
(optional)
XIN
ADDR
Specifications subject to change without notice
R
), then multiplying it up in the main loop through the feedback divider (N
– Rev. 3.0, Jan. 08
REFDSRC
Interface
(f
REF
VCXO
I
2
)
C
XCT[3:0],
XLVTEN
Px
Reference
REFDIV[11:0]
), we have the defining relationship for this mode. The equation for the output clock frequency (f
Divider
(N
R
)
Registers
REF
Control
Divider
VCXO
ROM
) can be either supplied by the VCXO or applied to the REF pin.
PDREF
PDFBK
Figure 25: Block Diagram: Stand-Alone Clock Generation
f
REF
Frequency
XLROM[2:0]
Detector
Phase-
=
Frequency
Detector
14318181
f
Phase-
XLPDEN,
XLSWAP
Divider
CLK
Feedback
FBKDIV[14:0]
=
DOWN
UP
(N
CRYSTAL LOOP
Charge
MLCP[1:0]
Pump
F
f
)
REF
DOWN
UP
35
Charge
.
XLCP[1:0]
Pump
81
⎛
⎜ ⎜
⎝
FBKDSRC[1:0]
N
N
=
Controlled
Oscillator
F
R
Voltage
VCOSPD,
OSCTYPE
2
⎞
⎟ ⎟
⎠
⎛
⎜ ⎜
⎝
5
×
N
1
3
Px
2
11
(f
×
⎞
⎟ ⎟
⎠
VCO
OM[1:0]
5
)
7
×
MAIN LOOP
EXTLF
Gobbler
Clock
7
Internal
GBL
Loop
Filter
1
LFTC
F
), and finally dividing the main loop output
POST3[1:0]
POST2[1:0]
POST1[1:0]
Divider
(N
Post
Px
)
Detect
STAT[1:0]
FS6131
Lock
CMOS/PECL
Output
CMOS
C
R
LF
LF
C
EXTLF
(optional)
LOCK/
IPRG
(optional)
CLKP
CLKN
LP
R
IPRG
(f
CLK
)
Data Sheet
CLK
)