fs6131 AMI Semiconductor, Inc., fs6131 Datasheet - Page 39

• Manufacturer Part Number: fs6131
• Description: Fs6131-01g Programmable Line Lock Clock Generator Ic
• Manufacturer: AMI Semiconductor, Inc.

FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC
14.0 Device Application: Genlocking
Genlocking refers to the process of synchronizing the horizontal sync pulses (HSYNC) of a target graphics system to the HSYNC of a
source graphics system. In a genlocked mode, the FS6131 increases (or decreases) the frequency of the VCO until the FBK input is
frequency matched and phase-aligned to the frequency applied to the REF input. Since the feedback divider is within the graphics
system and the graphics system is the source of the signal applied to the FBK input of the FS6131, the graphics system is effectively
synchronized to the REF input as shown in Figure 27.
To configure the FS6131 for genlocking, the REF input (pin 12) and the FBK input (pin 13) are switched directly onto the feedback input
of the PFD. The reference and feedback dividers are not used.
The output clock frequency is:
The only remaining task is to select a post divider modulus (N
14.1 Example Calculation
A Visual BASIC program is available to completely program the FS6131 based on the given parameters.
The FS6131 is being used to genlock an LCD projection panel system to a VGA card-generated HSYNC. The total number of pixel
clocks generated by the VGA card, known as the horizontal total, are 800. Therefore, the LCD panel graphics system that is clocked by
the FS6131 is set to divide the output clock frequency (f
AMI Semiconductor
www.amis.com
Reference
HSYNC
(optional)
XOUT
REF
FBK
SCL
SDA
XTUNE
(optional)
XIN
ADDR
Specifications subject to change without notice
– Rev. 3.0, Jan. 08
REFDSRC
Interface
(f
CLK
VCXO
I
2
)
C
XCT[3:0],
XLVTEN
Reference
REFDIV[11:0]
Divider
(N
R
)
Registers
Control
Divider
System HSYNC
VCXO
ROM
PDREF
PDFBK
f
CLK
Frequency
XLROM[2:0]
Detector
Phase-
Figure 27: Block Diagram: Genlocking
Frequency
Detector
=
Phase-
XLPDEN,
XLSWAP
Divider
Feedback
CLK
FBKDIV[14:0]
f
) by 800. The input HSYNC reference frequency (f
Video Graphics System
HSYNC
DOWN
UP
(N
CRYSTAL LOOP
Charge
MLCP[1:0]
Pump
Px
F
)
) that allows the VCO frequency to be within its nominal range.
DOWN
UP
39
×
Charge
XLCP[1:0]
Pump
FBKDSRC[1:0]
horizontal
Controlled
Oscillator
Voltage
OSCTYPE
VCOSPD,
(f
VCO
OM[1:0]
Clock In
total
)
Gobbler
EXTLF
Clock
MAIN LOOP
Internal
GBL
Loop
Filter
LFTC
POST3[1:0],
POST2[1:0],
POST1[1:0]
Divider
(N
Post
Px
)
Detect
STAT[1:0]
FS6131
Lock
CMOS/PECL
Output
HSYNC
CMOS
) is 15kHz.
C
R
LF
LF
C
EXTLF
(optional)
LOCK/
IPRG
(optional)
CLKP
CLKN
LP
R
IPRG
(f
(f
CLK
CLK
)
)
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