fs6131 AMI Semiconductor, Inc., fs6131 Datasheet - Page 32

• Manufacturer Part Number: fs6131
• Description: Fs6131-01g Programmable Line Lock Clock Generator Ic
• Manufacturer: AMI Semiconductor, Inc.

FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC
Table 21: Sample Text Output
11.0 Applications Information
A signal reflection will occur at any point on a PC-board trace where impedance mismatches exist. Reflections cause several
undesirable effects in high-speed applications, such as an increase in clock jitter and a rise in electromagnetic emissions from the
board. Using a properly designed series termination on each high-speed line can alleviate these problems by eliminating signal
reflections.
11.1 PECL Output Mode
If a PECL interface is desired, the transmission line must be terminated using a Thévenin, or dual, termination. The output stage can
only sink current in the PECL mode, and the amount of sink current is set by a programming resistor on the LOCK/IPRG pin. Source
current is provided by the pull-up resistor that is part of the Thévenin termination.
Thévenin termination uses two resistors per transmission line. The parallel resistance of the termination resistors should be sized to
equal the transmission line impedance, taking into account the driver sink current, the desired rise and fall times, and the VIH and VIL
specifications of the load.
AMIS - FS6131 Solution Text File
Created: Today’s Date, Today’s Time
Line-Locked / Genlock Mode
Desired Multiple = 800
Source = 0.0315MHz Reference Pin
External Loop Filter C1 = 4700pF R = 47kOhms
Crystal Oscillator Voltage Tune Disabled
Output Stage = CMOS
Reference Divider = 1
Feedback Divider = 800
Post Divider
Charge Pump (uA) = 10
EXTLF
XLVTEN
XCT
CMOS
Register 0 = 1H (1)
Register 1 = 40H (64)
Register 2 = 2H (2)
Register 3 = 20H (32)
Register 4 = 3H (3)
Register 5 = 26H (38)
Register 6 = 0H (0)
Register 7 = 17H (23)
AMI Semiconductor
www.amis.com
= 7
= 1
= 1
= 4
= 0
Specifications subject to change without notice
– Rev. 3.0, Jan. 08
R
i
PECL Mode Output
IPRG
from
PLL
Figure 22: Thévenin Termination (PECL)
{
CLKN
CLKP
32
z
O
z
z
L
L
R
R
p1
p2
V
CC
R
R
n1
n2
V
CC
LOAD
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