fs6131 AMI Semiconductor, Inc., fs6131 Datasheet - Page 38

• Manufacturer Part Number: fs6131
• Description: Fs6131-01g Programmable Line Lock Clock Generator Ic
• Manufacturer: AMI Semiconductor, Inc.

FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC
However, the 31.5kHz line reference signal is too low in frequency for the internal loop filter to be used. A series combination of a
0.015mF capacitor and a 15kW resistor from power (V
in parallel with the combination may improve the filter performance.
For the best PLL performance, program the post divider modulus to allow the VCO to operate at a nominal frequency that is at least
70MHz but less than 230MHz. The VCO frequency (f
Setting the post divider equal to four (N
to avoid divider values from becoming too large. These settings place the VCO frequency at about 100MHz.
Calculate the ideal charge pump current (I
where R
either:
See Table 15 for more information on the VCO range. With f
the charge pump current is 39.3mA. A 220pF cap across the entire loop filter is also helpful.
13.2 Example Programming
To generate 800 pixel clocks between HSYNC pulses occurring on the line reference signal every 31.5kHz, program the following (refer
to Figure 26):
• Clear the OSCTYPE bit to 0
• Turn off the crystal oscillator via XLROM=7
• Set the PFD inputs to select the REF pin and the feedback divider via PDREF=1 and PDFBK=0
• Set the feedback divider input to select the post divider via FBKDSRC=0
• Set the feedback divider (N
• Set N
• Select the external loop filter via EXTLF=1
• Set XLVTEN=0 and XLPDEN=1 to disable the VCXO fine tune and the crystal loop phase frequency detector
• Set VCOSPD=1 to select the VCO low speed range
• Set MLCP[1:0] to 3 to select the 32mA range
The output clock frequency f
this application.
AMI Semiconductor
www.amis.com
P1
lf
=4, N
A
A
is the external loop filter series resistor, C
VCO
VCO
=125MHz/V if the high range is selected, or
=75MHz/V if the low range is selected.
P2
=1 and N
Specifications subject to change without notice
– Rev. 3.0, Jan. 08
P3
=1 for a combined post divider modulus of N
F
CLK
) to a modulus of 800 (the desired number of pixel clocks per line) via FBKDIV[14:0]
is 25.175MHz, with an internal VCO frequency of 100.8MHz. Note that the crystal loop was unused in
Px
=4) is a reasonable solution, although there are a number of values that will work. Try to keep
pump
) as
lf
I
is the external loop filter series capacitor and A
pump
VCO
f
DD
VCO
) can be calculated by
) to the EXTLF pin provides an external loop filter. A 100pF to 220pF capacitor
=
N
=
F
hsync
15
f
f
×
HSYNC
HSYNC
=31.5kHz, C
kHz
N
38
Px
×
<
×
Px
N
5000
=4 via POST1[1:0], POST2[1:0] and POST3[1:0].
R
2
F
lf
2
N
C
×
lf
F
=0.015mF, R
lf
N
N
A
Px
VCO
Px
lf
=15kW, N
VCO
F
=800, N
is the VCO gain. The VCO gain is
Px
=4, and A
VCO
=125MHz/V,
Data Sheet