z16f2811 ZiLOG Semiconductor, z16f2811 Datasheet - Page 158

• Manufacturer Part Number: z16f2811
• Description: High Performance Microcontrollers
• Manufacturer: ZiLOG Semiconductor

™
ZNEO
Z16F Series
Product Specification
144
In addition to the LMST, LSLV, and ABEN bits in the LIN control register, a LinState[1:0]
field exists that defines the current state of the LIN logic. This field is initially set by the
software. In the LIN SLAVE mode, the LinState field is updated by hardware as the slave
moves through the Wait for Break, AutoBaud, and Active states.
The noise filter is also required to be enabled and configured when interfacing to
a LIN bus.
LIN MASTER Mode Operation
LIN MASTER mode is selected by setting the bits LMST = 1, LSLV = 0, ABEN = 0,
LinState[1:0] = 11b. If the LIN bus protocol indicates the bus is required go into the LIN
Sleep state, the LinState[1:0] bits must be set =
by the software.
00b
The Break is the first part of the message frame transmitted by the master, consisting of at
least 13 bit periods of logical zero on the LIN bus. During initialization of the LIN master,
the duration (in bit times) of the Break is written to the TxBreakLength field of the LIN
control register. The transmission of the Break is performed by setting the
bit in the
SBRK
control 0 register. The LIN-UART starts the Break once the
bit is set and any
SBRK
character transmission currently underway has completed. The
bit is deasserted by
SBRK
hardware once the break is completed.
The Synch character is transmitted by writing a
to the transmit data register (
55H
TDRE
must be 1 before writing). The Synch character is not transmitted by the hardware until
after the Break is complete.
The Identifier character is transmitted by writing the appropriate value to the transmit data
register (
must be 1 before writing).
TDRE
If the master is sending the response portion of the message, these data and checksum
characters are written to the transmit data register when the TDRE bit asserts.
If the transmit data register is written after TDRE asserts, but before TXE asserts, the
hardware inserts one or two Stop bits between each character as determined by the Stop bit
in the control0 register. Additional idle time occurs between characters if TXE asserts
before the next character is written.
LIN Sleep Mode
While the LIN bus is in the Sleep state, the CPU is in either low power STOP mode, in
HALT mode, or in normal operational state. Any device on the LIN bus issues a Wake-up
message (transmit an
character) if it needs the master to initiate a LIN message frame.
80H
Following the Wake-up message, the master wakes up and initiates a new message.
If the CPU is in STOP mode, the LIN-UART is not active and the Wake-up message must
be detected by a GPIO edge detect Stop Mode Recovery. The duration of the Stop Mode
Recovery sequence may preclude making an accurate measurement of the Wake-up
message duration.
PS022006-0207
P R E L I M I N A R Y
LIN-UART