z16f2811 ZiLOG Semiconductor, z16f2811 Datasheet - Page 208

• Manufacturer Part Number: z16f2811
• Description: High Performance Microcontrollers
• Manufacturer: ZiLOG Semiconductor

Table 102. ESPI Status Register (ESPISTAT)
PS022006-0207
R/W* = Read access. Write a 1 to clear the bit to 0.
RESET
FIELD
ADDR
BITS
R/W
ESPI Status Register
TDRE
R
7
0
The ESPI Status register (see
revert to their Reset state, if the ESPI is disabled.
TDRE—Transmit Data Register Empty
0 = Transmit data register is full or ESPI is disabled.
1 = Transmit data register is empty. A write to the ESPI (Transmit) Data register clears this
TUND—Transmit Underrun
0 = A Transmit Underrun error has not occurred.
1 = A Transmit Underrun error has occurred.
COL—Collision
0 = A Multi-Master collision (mode fault) has not occurred.
1 = A Multi-Master collision (mode fault) has been detected.
ABT—Slave mode transaction abort
This bit is set if the ESPI is configured in Slave mode, a transaction is occurring and SS
deasserts before all bits of a character have been transferred as defined by the NUMBITS
field of the ESPIMODE register. This bit is also be set in Slave mode by an SCK monitor
timeout (MMEN = 0, BRGCTL = 1).
0 = A Slave mode transaction abort has not occurred.
1 = A Slave mode transaction abort has been detected.
ROVR—Receive Overrun
0 = A Receive Overrun error has not occurred.
1 = A Receive Overrun error has occurred.
RDRF—Receive Data Register Full
0 = Receive Data register is empty.
1 = Receive Data register is full. A read from the ESPI (Receive) Data register clears
this bit.
bit.
TUND
R/W*
6
0
R/W*
COL
5
0
P R E L I M I N A R Y
Table
R/W*
ABT
4
0
102) indicates the current state of the ESPI. All bits
FF_E264H
ROVR
R/W*
3
0
Enhanced Serial Peripheral Interface
RDRF
R
2
0
Product Specification
ZNEO
TFST
1
R
0
™
Z16F Series
SLAS
R
0
1
194