z16f2811 ZiLOG Semiconductor, z16f2811 Datasheet - Page 283

• Manufacturer Part Number: z16f2811
• Description: High Performance Microcontrollers
• Manufacturer: ZiLOG Semiconductor

PS022006-0207
DMA Water Mark
DMA Peripheral Interface signals
Buffer Closure
When operating in direct mode the DMAxLAR[23:16] byte is used as a water mark inter-
rupt. If these bits are set to any value other than 0, they are compared to the low byte of the
decremented transfer length during a transfer. If the
DMAxTXLN[15:8] is zero and DMAxTXLN[7:0] == DMAxLAR[23:16] then an inter-
rupt is generated. This function allows the DMA channel to generate an interrupt prior to
the buffer becoming empty.
The DMA uses two input signals, four output signals and two 4-bit buses to communicate
with the peripherals. The input signals are Request (REQ) and Request EOF. The output
signals are Acknowledge (ACK), Command Valid (CMDVLD), End of Frame (EOF-
SYNC) and Read Status (RDSTAT). The two 4-bit busses are Command Bus (CMDBUS)
and Stat Bus (STATBUS).
A DMA transfer is initiated with the Request (REQ). When the DMA is servicing a
Request from a peripheral it will assert its acknowledge signal (ACK) to let the peripheral
know that a transfer is in progress. When the first byte of the transfer is written the CMD-
VLD is asserted and the command bits are placed on the CMDBUS. The peripheral needs
to latch the command from the bus when it sees this combination of signals.
If the
SYNC signal is asserted on the last data transfer to the peripheral to let it know that this is
the last byte in the frame.
After receiving the EOFSYNC signal the peripheral need to assert the Request EOF signal
to the DMA to let the DMA know that the descriptor is closed. This could be immediately
or at some later time if the data transferred still needs to be processed. For peripherals,
which do not support a Request EOF, the EOFSYNC is tied to Request EOF to terminate
the transfer.
Once the Request EOF is asserted the DMA closes the descriptor. The DMA asserts the
ACK and RDSTAT signal, if the descriptor EOF bit is set. The peripheral, if it has status,
places it on the STATBUS. This status is then placed in the descriptor and DMA status bits
when it is closed.
If a peripheral needs to close a descriptor because of an error or the end of a packet is
reached then it asserts it is Request EOF. If the transfer length is not zero, then the DMA
will set the EOF bit, close the descriptor and generate an interrupt.
A DMA buffer closure is requested in two ways. The first is when the transfer length
reaches zero. The second is when the DMA receives a request end of frame from the
peripheral. When either of these cases occur, the DMA begins closure of the buffer.
EOF
bit is set on the current buffer, when the TXLN decrements to zero the EOF-
P R E L I M I N A R Y
IEOB
bit is set and the upper byte of
Product Specification
ZNEO
™
DMA Controller
Z16F Series
269