z16f2811 ZiLOG Semiconductor, z16f2811 Datasheet - Page 281

• Manufacturer Part Number: z16f2811
• Description: High Performance Microcontrollers
• Manufacturer: ZiLOG Semiconductor

PS022006-0207
DMA Control Bit Definitions
Table 141. Linked list Descriptor
The following paragraphs explain the control bits of each DMA channel.
DMAxEN:
This bit if set by the CPU enables the DMA channel for direct operation. Direct operation
uses the addresses and transfer length, which has been directly written to the DMA
Channel by software.
If this bit is set by a descriptor read then linked list mode is enabled. Linked list operation
starts when an address is written to the DMAxLAR. This write causes the DMA to read in
the descriptor control value and addresses and place them in the DMA Channel.
LOOP
If the DMA is in linked list mode and this bit is set to one, it prevents the DMA from
updating the descriptor when the buffer is closed. This bit is set to allow lists to loop on
themselves without software intervention.
TXSIZE
The TXSIZE bits sets the width of the transfer.
00 = 8-bit bytes are transferred on each DMA transfer. The destination and source
addresses increment or decrement by one for each transfers if the DSTCTL and/or SRC-
CTL is selected for increment or decrement. The transfer length is decremented by one.
This allows 64 K bytes to be transferred.
01 = A 16-bit word is transferred on each DMA transfer. The destination and source
addresses increment or decrement by two if the DSTCTL and/or SRCCTL is selected for
increment or decrement. In word mode the transfer length is still decremented by one. This
allows 64 K words to be transferred.
10 = A 32-bit quad is transferred on each DMA transfer. The destination and source
addresses increment or decrement by four if the DSTCTL and/or SRCCTL is selected for
Address
LAR
LAR + 02H
LAR + 04H
LAR + 08H
LAR + 0CH
LAR High
Even
CONTROL
TXLN
DAR High
SAR High
P R E L I M I N A R Y
Product Specification
ZNEO
™
DMA Controller
Z16F Series
267