z16f2811 ZiLOG Semiconductor, z16f2811 Datasheet - Page 344
z16f2811
Manufacturer Part Number
z16f2811
Description
High Performance Microcontrollers
Manufacturer
ZiLOG Semiconductor
Datasheet
1.Z16F2811.pdf
(383 pages)
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Table 181. Oscillator Divide Register (OSCDIV)
* The reset value is 08H if the option bit LPOPT is 0.
PS022006-0207
Bit Position
[3]
WDFEN
[2]
FLPEN
[1:0]
SCKSEL
Bit Position
[7:0]
DIV
RESET
FIELD
ADDR
BITS
R/W
Oscillator Divide Register
00H to FFH
7
Value (H) Description
Value (H)
The Oscillator Divide register (OSCDIV) provides the value to divide the system clock by.
The Oscillator Divide Register must be unlocked before writing. Writing the two-step
sequence
The register locks after completion of a register write to the OSCDIV.
00
01
10
11
0
1
0
1
E7H
6
Oscillator Divide
00H - divider is disabled, all other entries are the divide value for scaling the
system clock.
Description
WDT Oscillator Failure Detection Enable
Failure detection of WDT oscillator is disabled.This bit is cleared
automatically if a WDT oscillator failure is detected.
Failure detection of WDT oscillator is enabled
Flash Low Power Mode Enable
Flash Low Power Mode is disabled.
Flash Low Power Mode is enabled. The Flash will be powered down during
idle periods of the clock and powered up during Flash reads. This bit must
only be set if the frequency of the primary oscillator source is 8 MHz or lower.
The reset value of this bit is controlled by the LPOPT option bit during reset.
System Clock Oscillator Select
Internal precision oscillator functions as system clock at 5.6 MHz
Crystal oscillator or external clock driver functions as system clock
Reserved
Watchdog Timer oscillator functions as system clock
followed by
5
P R E L I M I N A R Y
18H
to the Oscillator Control register address unlocks it.
4
FF_E0A1H
00H*
R/W
DIV
3
2
Product Specification
ZNEO
1
Oscillator Control
™
Z16F Series
0
330
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