s908ab32ag0cfue Freescale Semiconductor, Inc, s908ab32ag0cfue Datasheet - Page 145

• Manufacturer Part Number: s908ab32ag0cfue
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

MC68HC908AB32
Freescale Semiconductor
NOTE:
—
Rev. 1.1
PLLIE — PLL Interrupt Enable Bit
PLLF — PLL Interrupt Flag Bit
The PLLF bit should not be inadvertently cleared. Any read or read-
modify-write operation on the PLL control register clears the PLLF bit.
PLLON — PLL On Bit
BCS — Base Clock Select Bit
This read/write bit enables the PLL to generate an interrupt request
when the LOCK bit toggles, setting the PLL flag, PLLF. When the
AUTO bit in the PLL bandwidth control register (PBWC) is clear,
PLLIE cannot be written and reads as 0. Reset clears the PLLIE bit.
This read-only bit is set whenever the LOCK bit toggles. PLLF
generates an interrupt request if the PLLIE bit is set also. PLLF
always reads as 0 when the AUTO bit in the PLL bandwidth control
register (PBWC) is clear. The PLLF bit should be cleared by reading
the PLL control register. Reset clears the PLLF bit.
This read/write bit activates the PLL and enables the VCO clock,
CGMVCLK. PLLON cannot be cleared if the VCO clock is driving the
base clock, CGMOUT (BCS = 1). See
Circuit. Reset sets this bit so that the loop can stabilize as the MCU
is powering up.
This read/write bit selects either the crystal oscillator output,
CGMXCLK, or the VCO clock, CGMVCLK, as the source of the CGM
output, CGMOUT. CGMOUT frequency is one-half the frequency of
the selected clock. BCS cannot be set while the PLLON bit is clear.
After toggling BCS, it may take up to three CGMXCLK and three
CGMVCLK cycles to complete the transition from one source clock to
1 = PLL interrupts enabled
0 = PLL interrupts disabled
1 = Change in lock condition
0 = No change in lock condition
1 = PLL on
0 = PLL off
Clock Generator Module (CGM)
9.4.3 Base Clock Selector
Clock Generator Module (CGM)
Technical Data
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