s908ab32ag0cfue Freescale Semiconductor, Inc, s908ab32ag0cfue Datasheet - Page 181

• Manufacturer Part Number: s908ab32ag0cfue
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

11.6 Interrupts
11.7 Low-Power Modes
MC68HC908AB32
Freescale Semiconductor
—
Rev. 1.1
Setting MS2B links channels 2 and 3 and configures them for buffered
PWM operation. The TIMA channel 2 registers (TACH2H:TACH2L)
initially control the PWM output. TIMA channel 2 status and control
register (TASC2) controls and monitors the PWM signal from the linked
channels. MS2B takes priority over MS2A.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on
TIMA overflows. Subsequent output compares try to force the output to
a state it is already in and have no effect. The result is a 0% duty cycle
output.
Setting the channel x maximum duty cycle bit (CHxMAX) and clearing
the TOVx bit generates a 100% duty cycle output. See
Channel Status and Control
The following TIMA sources can generate interrupt requests:
The WAIT and STOP instructions puts the MCU in low-power-
consumption standby modes.
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TIMA overflow flag (TOF) — The TOF bit is set when the TIMA
counter value rolls over to $0000 after matching the value in the
TIMA counter modulo registers. The TIMA overflow interrupt
enable bit, TOIE, enables TIMA overflow CPU interrupt requests.
TOF and TOIE are in the TIMA status and control register.
TIMA channel flags (CH3F–CH0F) — The CHxF bit is set when an
input capture or output compare occurs on channel x. Channel x
TIM CPU interrupt requests are controlled by the channel x
interrupt enable bit, CHxIE. Channel x TIM CPU interrupt requests
are enabled when CHxIE= 1. CHxF and CHxIE are in the TIMA
channel x status and control register.
Timer Interface Module A (TIMA)
Registers.
Timer Interface Module A (TIMA)
11.10.4 TIMA
Technical Data
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