s908ab32ag0cfue Freescale Semiconductor, Inc, s908ab32ag0cfue Datasheet - Page 330

• Manufacturer Part Number: s908ab32ag0cfue
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Input/Output (I/O) Ports
17.8.2 Data Direction Register F (DDRF)
Technical Data
330
NOTE:
Address:
PTF[7:0] — Port F Data Bits
TACH[3:2] and TBCH[3:0] — Timer channel I/O bits
Data direction register F (DDRF) does not affect the data direction of
port F pins that are being used by TIMA and TIMB. However, the DDRF
bits always determine whether reading port F returns the states of the
latches or the states of the pins. See
Data direction register F determines whether each port F pin is an input
or an output. Writing a logic 1 to a DDRF bit enables the output buffer for
the corresponding port F pin; a logic 0 disables the output buffer.
DDRF[7:0] — Data Direction Register F Bits
Reset:
Read:
Write:
These read/write bits are software programmable. Data direction of
each port F pin is under the control of the corresponding bit in data
direction register F. Reset has no effect on port F data.
The PTF5/TBCH1–PTF0/TACH2 pins are the TIMA and TIMB input
capture/output compare pins. The edge/level select bits,
ELSxB:ELSxA, determine whether the PTF5/TBCH1–PTF0/TACH2
pins are timer channel I/O pins or general-purpose I/O pins. See
11.10.4 TIMA Channel Status and Control Registers
TIMB Channel Status and Control
These read/write bits control port F data direction. Reset clears
DDRF[7:0], configuring all port F pins as inputs.
1 = Corresponding port F pin configured as output
0 = Corresponding port F pin configured as input
DDRF7
$000D
Bit 7
Figure 17-19. Data Direction Register F (DDRF)
0
Input/Output (I/O) Ports
DDRF6
6
0
DDRF5
5
0
DDRF4
4
0
Table
Registers.
DDRF3
3
0
17-7.
MC68HC908AB32
DDRF2
Freescale Semiconductor
2
0
DDRF1
and
1
0
—
12.10.4
Rev. 1.1
DDRF0
Bit 0
0