s908ab32ag0cfue Freescale Semiconductor, Inc, s908ab32ag0cfue Datasheet - Page 160

• Manufacturer Part Number: s908ab32ag0cfue
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Monitor ROM (MON)
10.4.1 Entering Monitor Mode
Technical Data
160
NOTE:
Table 10-1
Enter monitor mode by either
The MCU sends a break signal (10 consecutive logic 0s) to the host
computer, indicating that it is ready to receive a command. The break
signal also provides a timing reference to allow the host to determine the
necessary baud rate.
Monitor mode uses alternate vectors for reset, SWI, and break interrupt.
The alternate vectors are in the $FE page instead of the $FF page and
allow code execution from the internal monitor firmware instead of user
code. The COP module is disabled in monitor mode as long as V
Section 23. Electrical
or the RST pin. (See
more information on modes of operation.)
Holding the PTC3 pin low when entering monitor mode causes a bypass
of a divide-by-two stage at the oscillator. The CGMOUT frequency is
equal to the CGMXCLK frequency, and the OSC1 input directly
generates internal bus clocks. In this case, the OSC1 signal must have
a 50% duty cycle at maximum bus frequency.
Notes:
1. For V
•
•
IRQ Pin
V
V
TST
Executing a software interrupt instruction (SWI) or
Applying a logic 0 and then a logic 1 to the RST pin.
TST
TST
(1)
, see
shows the pin conditions for entering monitor mode.
Table 10-1. Monitor Mode Entry Conditions
Section 23. Electrical
Monitor ROM (MON)
1
1
Section 8. System Integration Module (SIM)
0
0
Specifications) is applied to either the IRQ pin
1
1
Specifications.
1
0
CGMXCLK ÷ 2
CGMVCLK ÷ 2
CGMXCLK
CGMOUT
or
MC68HC908AB32
Freescale Semiconductor
Bus Frequency
(CGMOUT ÷ 2)
CGMXCLK ÷ 4
CGMVCLK ÷ 4
CGMXCLK ÷ 2
or
TST
—
Rev. 1.1
(see
for