pcf2127a NXP Semiconductors, pcf2127a Datasheet - Page 39

• Manufacturer Part Number: pcf2127a
• Description: Integrated Rtc, Tcxo And Quartz Crystal
• Manufacturer: NXP Semiconductors

NXP Semiconductors
PCF2127A_1
Product data sheet
8.11.5 Pre-defined timers: second and minute interrupt
8.11.6 Clearing flags
If a new value of n is written before the end of the actual timer period, this value will take
immediate effect. It is not recommended to change n without first disabling the counter by
setting WD_CD[1:0] = 00. The update of n is asynchronous to the timer clock. Therefore
changing it on the fly could result in a corrupted value loaded into the countdown counter.
This can result in an undetermined countdown period for the first period. The countdown
value n will, however, be correctly stored and correctly loaded on subsequent timer
periods.
When the countdown timer flag CDTF is set, an interrupt signal on INT will be generated
provided that this mode is enabled. See
can be controlled.
When starting the countdown timer for the first time, only the first period will not have a
fixed duration. The amount of inaccuracy for the first timer period will depend on the
chosen source clock, see
Table 38.
At the end of every countdown, the timer sets the countdown timer flag (CDTF). CDTF
may only be cleared by software. The asserted CDTF can be used to generate an
interrupt (INT). The interrupt may be generated as a pulsed signal every countdown
period or as a permanently active signal which follows the condition of CDTF. TI_TP is
used to control this mode selection. The interrupt output may be disabled with the CDTIE
bit, see
When reading the timer, the actual countdown value is returned and not the initial value n.
Since it is not possible to freeze the countdown timer counter during read back, it is
recommended to read the register twice and check for consistent results.
PCF2127A has two pre-defined timers which are used to generate an interrupt either once
per second or once per minute. The pulse generator for the minute or second interrupt
operates from an internal 64 Hz clock. It is independent of the watchdog or countdown
timers.
The flags MSF, CDTF, AF and TSFx can be cleared by using the interface. To prevent one
flag being overwritten while clearing another, a logic AND is performed during the write
access. A flag is cleared by writing logic 0 whilst a flag is not cleared by writing logic 1.
Writing logic 1 will result in the flag value remaining unchanged.
Four examples are given for clearing the flags. Clearing the flags is made by a write
command, therefore bits labelled with
Timer source clock
4.096 kHz
64 Hz
1 Hz
1
⁄
60
•
•
Hz
‘-’ must be written with their previous values
‘WDTF’ is read only and has to be written with logic 0
Table
First period delay for timer counter
6.
Rev. 01 — 21 January 2010
Table
Minimum timer period
n
n
(n − 1) +
(n − 1) +
38.
1
1
⁄
⁄
64
64
Section 8.13.1.2
Hz
Hz
Integrated RTC, TCXO and quartz crystal
for details on how the interrupt
Maximum timer period
n + 1
n + 1
n +
n +
1
1
⁄
⁄
64
64
PCF2127A
Hz
Hz
© NXP B.V. 2010. All rights reserved.
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