pcf2127a NXP Semiconductors, pcf2127a Datasheet - Page 77

• Manufacturer Part Number: pcf2127a
• Description: Integrated Rtc, Tcxo And Quartz Crystal
• Manufacturer: NXP Semiconductors

NXP Semiconductors
23. Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10. PFO signal behavior when battery
Fig 11. PFO signal behavior when battery switch-over
Fig 12. PFO signal behavior when battery
Fig 13. Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . .25
Fig 14. Power-On Reset (POR) system. . . . . . . . . . . . . .26
Fig 15. Power-On Reset Override (PORO) sequence,
Fig 16. Power failure event due to battery discharge:
Fig 17. Data flow of the time function. . . . . . . . . . . . . . . .31
Fig 18. Access time for read/write operations . . . . . . . . .31
Fig 19. Alarm function block diagram. . . . . . . . . . . . . . . .32
Fig 20. Alarm flag timing diagram . . . . . . . . . . . . . . . . . .34
Fig 21. WD_CD[1:0] = 10: watchdog activates
Fig 22. WD_CD[1:0] = 11: watchdog activates
Fig 23. General countdown timer behavior . . . . . . . . . . .38
Fig 24. Timestamp detection with two push-buttons
Fig 25. Interrupt block diagram . . . . . . . . . . . . . . . . . . . .45
Fig 26. INT example for SI and MI when TI_TP is
Fig 27. INT example for SI and MI when TI_TP is
Fig 28. Example of shortening the INT pulse by
Fig 29. Example of shortening the INT pulse by
Fig 30. AF timing diagram . . . . . . . . . . . . . . . . . . . . . . . .49
Fig 31. STOP bit functional diagram . . . . . . . . . . . . . . . .52
Fig 32. STOP bit release timing . . . . . . . . . . . . . . . . . . . .52
Fig 33. Interface selection . . . . . . . . . . . . . . . . . . . . . . . .53
Fig 34. SDI, SDO configurations . . . . . . . . . . . . . . . . . . .54
Fig 35. Data transfer overview . . . . . . . . . . . . . . . . . . . . .54
Fig 36. SPI-bus write example . . . . . . . . . . . . . . . . . . . . .55
PCF2127A_1
Product data sheet
Block diagram of PCF2127A . . . . . . . . . . . . . . . . .3
Pin configuration for PCF2127A (SO20) . . . . . . . .4
Handling address registers . . . . . . . . . . . . . . . . . .6
Battery switch-over behavior in standard mode
with bit BIE logic 1 (enabled) . . . . . . . . . . . . . . . .18
Battery switch-over behavior in direct switching
mode with bit BIE logic 1 (enabled) . . . . . . . . . . .19
Battery switch-over circuit, simplified
block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Typical driving capability of V
with respect to the output load current I
Battery low detection behavior with bit
BLIE logic 1 (enabled) . . . . . . . . . . . . . . . . . . . . .22
Typical application of the extra power fail
detection function. . . . . . . . . . . . . . . . . . . . . . . . .22
switch-over is enabled in standard mode and
V
is enabled in direct switching mode and
V
switch-over is disabled. . . . . . . . . . . . . . . . . . . . .24
valid for both I
reset occurs . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
an interrupt when timed out . . . . . . . . . . . . . . . . .37
a reset pulse when timed out . . . . . . . . . . . . . . . .38
on one the TS pin (e.g. for tamper detection) . . .41
logic 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
logic 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
clearing the MSF flag . . . . . . . . . . . . . . . . . . . . . .48
clearing the CDTF flag . . . . . . . . . . . . . . . . . . . . .48
th(uvp)
th(uvp)
> (V
< V
BAT
BAT
. . . . . . . . . . . . . . . . . . . . . . . . . . . .24
2
, V
C-bus and SPI-bus . . . . . . . . . . .26
th(sw)bat
) . . . . . . . . . . . . . . . . . . .23
BBS
: (V
BBS
BBS
- V
Rev. 01 — 21 January 2010
DD
. . . . .21
)
Fig 37. SPI-bus read example. . . . . . . . . . . . . . . . . . . . . 55
Fig 38. Bit transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Fig 39. Definition of START and STOP conditions . . . . . 56
Fig 40. System configuration. . . . . . . . . . . . . . . . . . . . . . 57
Fig 41. Acknowledgement on the I
Fig 42. Bus protocol, writing to registers . . . . . . . . . . . . . 58
Fig 43. Bus protocol, reading from registers . . . . . . . . . . 58
Fig 44. Bus protocol, writing to RAM. . . . . . . . . . . . . . . . 59
Fig 45. Bus protocol, reading from RAM . . . . . . . . . . . . . 60
Fig 46. Device diode protection diagram of
Fig 47. I
Fig 48. I
Fig 49. Characteristic of frequency with respect to
Fig 50. SPI-bus timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Fig 51. I
Fig 52. Package outline SOT163-1 (SO20) . . . . . . . . . . 72
PCF2127A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
refer to 30 % and 70 % . . . . . . . . . . . . . . . . . . . . 71
DD
DD
2
C-bus timing diagram; rise and fall times
Integrated RTC, TCXO and quartz crystal
as a function of temperature . . . . . . . . . . . . . 65
as a function of V
DD
. . . . . . . . . . . . . . . . . . . . 66
PCF2127A
2
C-bus. . . . . . . . . . . . 57
© NXP B.V. 2010. All rights reserved.
77 of 79