pca82c200t NXP Semiconductors, pca82c200t Datasheet - Page 38

• Manufacturer Part Number: pca82c200t
• Description: 8-bit Microcontroller With On-chip Can
• Manufacturer: NXP Semiconductors

Philips Semiconductors
13.5.5
The contents of the Status Register reflects the status of the CAN-controller. The Status Register appears to the CPU
as a read only memory.
Table 36 Status Register (address 2)
Table 37 Description of the SR bits
1996 Jun 27
8-bit microcontroller with on-chip CAN
BIT
BS
7
7
6
5
4
3
2
1
0
S
TATUS
BS
ES
TS
RS
TCS
TBS
DO
RBS
R
SYMBOL
EGISTER
ES
6
(SR)
Bus Status (note 1). If the value of BS is:
Error Status. If the value of ES is:
Transmit Status (note 2). If the value of TS is:
Receive Status (note 2). If the value of RS is:
Transmission Complete Status (note 3). If the value of TCS is:
Transmit Buffer Access (note 3). If the value of TBS is:
Data Overrun (note 4). If the value of DO is:
Receive Buffer Status (note 5). If the value of RBS is:
HIGH (Bus-OFF), then the CAN-controller is not involved in bus activities.
LOW (Bus-ON), then the CAN-controller is involved in bus activities.
HIGH (error), then at least one of the Error Counters (see Section 13.6.10) has
reached the
CPU Warning limit.
LOW (ok), then both Error Counters have not reached the warning limit.
HIGH (transmit), then the CAN-controller is transmitting a message.
LOW (idle), then no message is transmitted.
HIGH (receive), then the CAN-controller is receiving a message.
LOW (idle), then no message is received.
HIGH (complete), then last requested transmission has been successfully completed.
LOW (incomplete), then previously requested transmission is not yet completed.
HIGH (released), then the CPU may write a message into the TBF.
LOW (locked), then the CPU cannot access the Transmit Buffer. A message is either
waiting for transmission or is in the process of being transmitted.
HIGH (overrun), then both Receive Buffers are full and the first byte of another
message should be stored.
LOW (absent), then no data overrun has occurred since the Clear Overrun command
was given.
HIGH (full), then this bit is set when a new message is available.
LOW (empty), then no message has become available since the last Release Receive
Buffer command bit was set.
TS
5
RS
4
38
TCS
3
FUNCTION
TBS
2
DO
1
Product specification
P8xCE598
RBS
0