pca82c200t NXP Semiconductors, pca82c200t Datasheet - Page 48

• Manufacturer Part Number: pca82c200t
• Description: 8-bit Microcontroller With On-chip Can
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 57 Description of the other DSCR2 bits
13.5.13.2 Data Field
The number of transferred data bytes is determined by the
Data Length Code. The first bit transmitted is the most
significant bit of data byte 1 at address 12.
13.5.14 R
The layout of the Receive Buffer and the individual bytes
correspond to the definitions given for the Transmit Buffer
layout, except that the addresses start at 20 instead of 10
(see Fig.15).
Table 58 The SFRs between CPU and CAN
Reserved bits are read as HIGH. R = Read; W = Write; R/W = Read/Write.
1996 Jun 27
CANADR
DBH
CANDAT
DAH
CANCON; Do not use a RMW instruction
D9H
CANSTA; The bit addresses of CANSTA (7 to 0) are DFH to D8H; do not use a RMW instruction
DFH to D8H R
ADDRESS
8-bit microcontroller with on-chip CAN
BIT
4
3
2
1
0
ECEIVE
RTR
DLC.3
DLC.2
DLC.1
DLC.0
ACCESS
R/W
R/W
R
W
W
SYMBOL
B
UFFER LAYOUT
DMA
CAND7
Reserved Reserved Reserved WUI
RX0A
BS
RAMA7
Remote Transmission Request. If the RTR bit is:
Data Length Code (DLC). The number of bytes (Data Byte Count) in the Data Field of a
message is coded by the Data Length Code. At the start of a Remote Frame transmission
the Data Length Code is not considered due to the RTR bit being HIGH (remote). This
forces the number of transmitted/received data bytes to be a logic 0. Nevertheless, the
Data Length Code must be specified correctly to avoid bus errors, if two CAN-controllers
start a Remote Frame transmission simultaneously. The range of the Data Byte Count is
0 to 8 bytes and coded as follows:
For reasons of compatibility no Data Byte Counts other than 0,1,2,....,8 should be used.
Data Byte Count
7
HIGH (remote), then the Remote Frame will be transmitted by the CAN-controller.
LOW (data), then the Data Frame will be transmitted by the CAN-controller.
Reserved AutoInc
CAND6
RX1A
ES
RAMA6
6
=
8DLC.3
CAND5
WUM
TS
RAMA5
5
+
48
4DLC.2
13.5.15 H
Via the four special registers CANADR, CANDAT,
CANCON and CANSTA the CPU has access to the
CAN-controller and also to the DMA-logic. Note that
CANCON and CANSTA have different meanings for a
Read and Write access.
CANA4
CAND4
SLP
RS
RAMA4
4
FUNCTION
+
2DLC.1
BIT
ANDLING OF THE
CANA3
CAND3
OI
COS
TCS
RAMA3
3
+
DLC.0
CANA2
CAND2
EI
RRB
TBS
RAMA2
CPU-CAN
2
CANA1
CAND1
TI
AT
DO
RAMA1
Product specification
INTERFACE
P8xCE598
1
CANA0
CAND0
RI
TR
RBS
RAMA0
0