pca82c200t NXP Semiconductors, pca82c200t Datasheet - Page 40

• Manufacturer Part Number: pca82c200t
• Description: 8-bit Microcontroller With On-chip Can
• Manufacturer: NXP Semiconductors

Philips Semiconductors
13.5.6
The Interrupt Register allows the identification of an interrupt source. When one or more bits of this register are set, a
CAN interrupt (SI01) will be indicated to the CPU. All bits are reset by the CAN-controller after this register is read by the
CPU. This register appears to the CPU as a read only memory.
Table 38 Interrupt Register (address 3)
Table 39 Description of the IR bits
Notes
1. Overrun Interrupt bit (if enabled) and Data Overrun bit (see Section 13.5.5) are set at the same time.
2. Receive Interrupt bit (if enabled) and Receive Buffer Status bit (see Section 13.5.5) are set at the same time.
1996 Jun 27
8-bit microcontroller with on-chip CAN
BIT
7
7
6
5
4
3
2
1
0
I
NTERRUPT
WUI
OI
EI
TI
RI
SYMBOL
R
6
EGISTER
(IR)
Reserved.
Reserved.
Reserved.
Wake-Up Interrupt. The value of WUI is set to:
Overrun Interrupt (note 1). The value of OI is set to:
Error Interrupt. The value of EI is set to:
Transmit Interrupt. The value of TI is set to:
Receive Interrupt (note 2). The value of RBS is set to:
HIGH (set), when the sleep mode is left. See Section 13.5.4.
LOW (reset), by a read access of the Interrupt Register by the CPU.
HIGH (set), if both Receive Buffers contain a message and the first byte of another
message should be stored (passed acceptance), and the Overrun Interrupt Enable is
HIGH (enabled).
LOW (reset), by a read access of the Interrupt Register by the CPU.
HIGH (set), on a change of either the Error Status or Bus Status bits, if the Error
Interrupt Enable is HIGH (enabled). See Section 13.5.5.
LOW (reset), by a read access of the Interrupt Register by the CPU.
HIGH (set), on a change of the Transmit Buffer Access from LOW to HIGH (released)
and
Transmit Interrupt Enable is HIGH (enabled).
LOW (reset), after a read access of the Interrupt Register by the CPU.
HIGH (set), when a new message is available in the Receive Buffer and the Receive
Interrupt Enable bit is HIGH (enabled).
LOW (reset) automatically by a read access of Interrupt Register by the CPU.
5
WUI
4
40
OI
3
FUNCTION
EI
2
TI
1
Product specification
P8xCE598
RI
0